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- Development2009-11-23 14:43:47 +0100
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- Knowledgebase
- FPGA Universe
- Tutorials
- Basic FPGA Tutorial - Vivado VHDL v2022.22015-12-18 19:35:36 +0100
- Basic FPGA Tutorial - Vivado Verilog v2022.22015-12-18 19:35:50 +0100
- Basic FPGA Tutorial - ISE v14.7, VHDL2015-12-18 19:36:15 +0100
- Basic Embedded System Design Tutorial v2022.22015-12-18 19:36:27 +0100
- Basic HLS Tutorial v2022.22016-10-18 16:09:36 +0200
- Basic SystemC Tutorial v2021.12020-07-05 19:00:06 +0200
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- Newsletter - September 20162016-09-16 10:39:32 +0200
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- FPGA Universe
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- soopendays 20122019-07-31 08:16:18 +0200
- Doulos
- Mathworks
- MATLAB Grundlagen2019-07-22 16:03:12 +0200
- Machine Learning mit MATLAB2017-06-27 11:02:03 +0200
- MATLAB Programmiertechniken2015-10-28 12:07:25 +0100
- Programmierung von AMD Xilinx Zynq SoCs mit MATLAB und Simulink2015-10-28 12:08:43 +0100
- Simulink zur System- und Algorithmenmodellierung2015-10-28 12:10:10 +0100
- Signalverarbeitung mit Simulink2015-10-28 12:09:39 +0100
- Objektorientierte Programmierung mit MATLAB2017-06-27 11:01:59 +0200
- National Instruments
- so-logic
- Yocto Basic2022-07-05 15:34:18 +0200
- Yocto Advanced2022-07-05 15:32:08 +0200
- Embedded System Basic2023-03-22 15:49:20 +0100
- Verification Tutorial Basic 2023-03-22 16:23:12 +0100
- FPGA Design with VHDL Basic2023-03-22 15:29:56 +0100
- FPGA Design with Verilog Basic2023-03-22 15:38:17 +0100
- FPGA Design with High Level Synthesis (HLS) Basic2023-03-22 16:04:20 +0100
- FPGA Design with SystemC Basic2023-03-22 16:10:27 +0100
- Art of FPGA Design
- Principles of FPGA Design2011-12-26 09:16:15 +0100
- Use Cases for FPGAs2011-12-26 09:41:24 +0100
- High Speed Serial IOs with FPGA2009-12-04 11:20:11 +0100
- Embedded System Ideas and Concepts2018-01-26 14:36:23 +0100
- Implementation of a digital Receiver with FPGAs2009-12-04 11:40:59 +0100
- High Speed DSP Design with FPGAs2018-01-26 14:38:11 +0100
- Embedded System Design with FPGAs2009-12-04 11:14:30 +0100
- High Level Synthesis
- C++2011-12-27 08:02:25 +0100
- SystemC TLM2011-12-27 10:13:09 +0100
- SystemC Concepts2011-12-27 16:00:25 +0100
- AMD Xilinx
- C++ for Adaptive SOC2023-05-20 09:08:01 +0200
- Architecture
- Designing with Versal AI Engine 1 - Architecture and Design Flow2023-03-17 10:41:03 +0100
- Designing with Versal AI Engine 2: Graph Programming with AI Engine Kernels2023-03-17 10:42:04 +0100
- Designing with Versal AI Engine 3: Kernel Programming and Optimization2023-03-17 10:43:54 +0100
- Developing AI Inference Solutions with the Vitis AI Platform2023-03-16 11:42:27 +0100
- Designing with the Versal Adaptive SoC: PCI Express Systems2023-03-17 10:45:13 +0100
- Designing with the Versal Adaptive SoC: Network on Chip2023-03-17 10:46:45 +0100
- Designing with the Versal Adaptive SoC: Architecture and Methodology2023-03-17 10:47:53 +0100
- Getting Started with the AMD Xilinx Versal Adaptive SoC Platform2023-03-16 11:01:50 +0100
- Designing with the Zynq UltraScale+ RFSoC2022-07-04 12:41:54 +0200
- Zynq SoC System Architecture2023-03-16 15:14:18 +0100
- Designing with the UltraScale and UltraScale+ Architectures2023-03-16 15:15:13 +0100
- Designing with AMD Xilinx 7 Series Families2016-08-03 09:43:39 +0200
- Designing with Spartan-6 and Virtex-6 Families2012-01-18 17:23:35 +0100
- Designing with Virtex-5 FPGA Family2023-03-16 15:16:52 +0100
- Spartan-6 with ISE Migration to 7 Series with Vivado2022-08-15 12:06:01 +0200
- Connectivity
- How to Design a High-Speed Memory Interface2023-03-16 15:21:10 +0100
- PCIe Protocol Overview2019-07-24 09:15:44 +0200
- Designing an Integrated PCI Express System2023-03-16 15:22:53 +0100
- Designing with Multi-Gigabit Serial I/O2023-03-16 15:23:47 +0100
- Designing with Ethernet MAC Controllers2023-03-16 15:24:54 +0100
- Signal Integrity and Board Design for AMD Xilinx FPGAs2023-03-16 11:24:46 +0100
- Designing with AMD Xilinx Serial Transceivers2023-03-16 11:26:07 +0100
- Designing with UltraScale FPGA Transceivers2023-03-16 15:25:50 +0100
- DSP
- Accelerating C, C++, OpenCL, and RTL Applications with the SDAccel Environment2023-03-16 15:27:04 +0100
- Essential DSP Implementation Techniques for Xilinx FPGAs2023-03-16 15:28:00 +0100
- DSP Design Using System Generator2023-03-16 15:29:03 +0100
- C-based Design: High-Level Synthesis with Vivado HLS2023-04-07 15:42:01 +0200
- C-based HLS Coding for Software Designers2012-09-28 12:16:03 +0200
- C-based HLS Coding for Hardware Designers2012-09-28 12:16:36 +0200
- Embedded
- Advanced SDSoC Development Environment and Methodology2018-06-13 11:45:32 +0200
- Developing AWS F1 Applications Using the SDAccel Environment2023-03-16 15:30:14 +0100
- Zynq All Programmable SoC System Architecture
- Embedded Open-Source Linux Development2023-03-16 15:37:02 +0100
- Embedded Design with PetaLinux Tools2023-03-16 15:37:42 +0100
- Migrating to the Vitis Embedded Software Development IDE Workshop2023-03-16 15:38:43 +0100
- Embedded Systems Design2023-03-16 15:39:50 +0100
- Advanced Features and Techniques of Embedded Systems Design2023-03-16 15:41:19 +0100
- Embedded Systems Software Design2023-03-16 15:43:14 +0100
- Advanced Features and Techniques of Embedded Systems Software Design 2023-03-16 15:40:41 +0100
- Embedded C/C++ SDSoC Development Environment and Methodology2023-03-16 15:44:02 +0100
- Zynq UltraScale+ MPSoC for the Hardware Designer 2018-11-11 14:05:23 +0100
- Zynq UltraScale+ MPSoC for the Software Developer2018-11-11 14:05:49 +0100
- Zynq UltraScale+ MPSoC for the System Architect 2019-07-24 10:23:12 +0200
- Developing and Optimizing Applications Using the OpenCL Framework for FPGAs2023-03-16 15:44:48 +0100
- Languages
- Designing with VHDL2023-03-17 10:09:49 +0100
- Advanced VHDL2023-03-17 10:10:21 +0100
- Designing with Verilog2023-03-17 10:11:09 +0100
- Designing with System Verilog2023-03-17 10:11:46 +0100
- Verification with System Verilog2018-11-11 14:11:25 +0100
- Tools
- Vitis Design flow2023-03-17 10:12:58 +0100
- Vivado Design Suite for ISE Project Navigator Users2023-03-17 10:15:27 +0100
- Designing FPGAs Using the Vivado Design Suite 12023-03-17 10:17:50 +0100
- Designing FPGAs Using the Vivado Design Suite 22023-03-17 10:18:20 +0100
- Designing FPGAs Using the Vivado Design Suite 32023-03-17 10:18:32 +0100
- Designing FPGAs Using the Vivado Design Suite 42023-03-17 10:19:09 +0100
- UltraFast Design Methodology2023-03-17 10:19:44 +0100
- Vivad Design Suite for ISE Software Project Navigator Users2023-03-17 10:20:18 +0100
- Vivado Advanced XDC and Static Timing Analysis for ISE Software Users2023-03-17 10:21:08 +0100
- Partial Reconfiguration Tools & Techniques2023-03-17 10:21:42 +0100
- Versal Live Online Workshop Compendium Complete
- Versal Compendium 1 : Architecture2023-03-17 10:22:26 +0100
- Versal Compendium 2 : High Speed Communication2021-08-18 22:47:40 +0200
- Versal Compendium 3 : AI Engine2021-09-08 10:44:21 +0200
- Vision KRIA SOM 2023-03-17 10:23:07 +0100
- Payment conditions2020-10-17 09:26:17 +0200
- Instruction2012-01-10 09:24:24 +0100
- IP Cores
- Interface Cores
- Ethernet
- 10/100/1000 Mb/s Ethernet
- 10/100/1000 Mb/s MAC Controller Core2019-05-08 12:50:02 +0200
- 1000BASE-X PCS Core2019-05-08 13:38:39 +0200
- 10/100/1000 Mb/s MAC Configurator Core2019-05-09 12:12:08 +0200
- Ethernet GMII Core2019-05-09 12:20:11 +0200
- Ethernet GMII2MII Core2019-05-09 12:55:21 +0200
- Ethernet GMII2RGMII Core2019-05-10 15:33:42 +0200
- 10G Ethernet
- 10G MAC Controller Core2019-05-08 13:50:25 +0200
- 10GBASE-R PCS Core2019-05-08 13:56:03 +0200
- 10 Gb/s Ethernet MAC Configurator Core2019-05-10 15:48:27 +0200
- Utility Ethernet Cores
- Ethernet Pause Generator Core2019-05-09 17:06:47 +0200
- Generator Checker Core2019-05-10 15:53:30 +0200
- Encryption Ethernet Cores
- AES Core2019-05-24 17:26:59 +0200
- Miscellaneous Ethernet Cores
- ARP Decoder Core2019-05-24 12:19:09 +0200
- ARP Encoder Core2019-05-24 12:19:25 +0200
- ARP Packet Core2019-05-24 12:19:48 +0200
- ARP Table Core2019-05-24 12:20:14 +0200
- Capture Register Core2019-05-24 12:20:41 +0200
- Error Statistics Core2019-05-24 12:21:00 +0200
- Ethernet Encoder Core2019-05-21 11:29:47 +0200
- Ethernet Decoder Core2019-05-20 17:15:48 +0200
- ICMP Decoder Core2019-05-24 12:22:06 +0200
- ICMP Encoder Core2019-05-24 12:22:32 +0200
- IP Decoder Core2019-05-24 12:22:52 +0200
- IP Encoder Core2019-05-24 12:23:13 +0200
- Ethertype2dest Core2019-05-24 12:23:31 +0200
- Network Packet FIFO Core2019-05-24 12:24:08 +0200
- Port2tdest Core2019-05-24 12:24:31 +0200
- Protocol2tdest Core2019-05-24 12:24:55 +0200
- Tdest2ethertype Core2019-05-24 12:26:31 +0200
- Tdest2port Core2019-05-24 12:26:49 +0200
- Protocol2protocol Core2019-05-24 12:27:07 +0200
- Time Stamp Counter Core2019-05-24 12:27:29 +0200
- UDP Decoder Core2019-05-24 12:27:55 +0200
- UDP Encoder Core2019-05-24 12:28:15 +0200
- UDP Register Handler Core2019-05-24 12:28:34 +0200
- 10/100/1000 Mb/s Ethernet
- Serial ATA
- SATA-II Host Controller Core2016-08-19 10:11:50 +0200
- SATA-III Host Controller Core2016-08-19 10:09:48 +0200
- Ethernet
- Machine Learning Cores
- Ensemble Classifiers Cores
- Ensemble Inference Cores
- Decision Tree Ensemble Inference Core2011-01-15 22:22:15 +0100
- Ensemble Evaluation Cores
- Decision Tree Ensemble Evaluation Core - Sequential Evaluation using Pipelined Architecture2010-11-20 14:50:36 +0100
- Decision Tree Ensemble Evaluation Core - Parallel Evaluation using Pipelined Architecture2010-11-20 14:51:18 +0100
- Decision Tree Ensemble Evaluation Core - Sequential Evaluation using Serial Architecture2010-11-20 14:54:00 +0100
- Decision Tree Ensemble Evaluation Core - Parallel Evaluation using Serial Architecture2010-11-20 14:55:23 +0100
- Combination Rules Cores
- Behavior Knowledge Space Core - Parallel Architecture2010-11-20 14:56:13 +0100
- Behavior Knowledge Space Core - Serial Architecture2010-11-20 14:56:40 +0100
- Weighted Majority Voting Core - Parallel Architecture2010-11-20 14:57:16 +0100
- Majority Voting Core - Parallel Architecture2010-11-20 14:57:51 +0100
- Majority Voting Core - Serial Architecture2010-11-20 14:58:16 +0100
- Ensemble Inference Cores
- Decision Trees Cores
- Decision Tree Inference Core2010-11-20 14:58:43 +0100
- Decision Tree Core using Serial Architecture2010-11-20 14:59:20 +0100
- Decision Tree Core using Pipelined Architecture2010-11-20 14:59:53 +0100
- Ensemble Classifiers Cores
- Processor and Microcontroller Cores
- 8051 Microcontroller Cores2011-01-16 09:52:01 +0100
- Finished and IP Cores Under Development2016-08-18 17:11:11 +0200
- Interface Cores
- Customers