Designing FPGAs Using the Vivado Design Suite 3

Learn how to effectively employ timing closure techniques. This course includes: Demonstrating timing closure techniques such as baselining, pipelining, and synchronization circuits Showing optimum HDL coding techniques that help with design timing closure Illustrating the advanced capabilities of the Vivado™ logic analyzer to debug a design

Event Schedule

Virtual Learning Environment (Online)
  • 14.10. - 15.10.2025 09:00-17:00 — € 1,700.00 excl. VAT Add to cart
  • 15.07. - 16.07.2025 09:00-17:00 — € 1,700.00 excl. VAT Add to cart
Request on-demand event: Click here.

Partner

Xilinx
Updated at: 2024-10-31 15:07:27 +0100to the top