Designing with Versal AI Engine 1: Architecture and Design Flow

This course describes the AMD Versalâ„¢ AI Engine architecture, the data communications within an AI Engine array and between the PL and AI Engines, how to program the AI Engines (single kernel programming and multiple ...

Event Schedule

so-logic (top1) (Austria)
  • 02.12. - 03.12.2024 09:00-17:00 — € 1,600.00 excl. VAT Add to cart
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Partner

Xilinx
Updated at: 2024-10-31 18:42:30 +0100to the top