Admin >>
Customer login
  • so-logic
  • Vision KRIA SOM Workshop
  • sozius
  • Activities
  • Knowledgebase
  • Trainings
  • IP Cores
  • Customers
  • Sitemap

Trainings

  • soopendays 2012
  • Search
  • Schedule
  • In-house Training
  • Create attendant account
  • Doulos
  • Mathworks
  • National Instruments
  • so-logic
  • FPGA Design with SystemC Basic
  • FPGA Design with VHDL Basic
  • FPGA Design with Verilog Basic
  • FPGA Design with High Level Synthesis HLS Basic
  • Verification Tutorial Basic
  • Embedded System Basic
  • Yocto Advanced
  • Yocto Basic
  • Xilinx
    • Architecture
    • Connectivity
      • How to Design a High-Speed Memory Interface
      • PCIe Protocol Overview
      • Designing an Integrated PCI Express System
      • Designing with Multi-Gigabit Serial I/O
      • Designing with Ethernet MAC Controllers
      • Signal Integrity and Board Design for Xilinx FPGAs
      • Designing with Xilinx Serial Transceivers
      • Designing with UltraScale FPGA Transceivers
    • DSP
    • Embedded
    • Languages
    • Tools
    • Versal Live Online Workshop Compendium Complete
    • Vision KRIA SOM
    • Designing FPGAs with Xilinx Vivado Tools
    • High-Level Synthesis with Vitis HLS
    • RFSoc and Yocto for FPGA
  • Payment conditions
  • Shopping Cart
  • Instruction

Connectivity

Courses

  • How to Design a High-Speed Memory Interface
  • PCIe Protocol Overview
  • Designing an Integrated PCI Express System
  • Designing with Multi-Gigabit Serial I/O
  • Designing with Ethernet MAC Controllers
  • Signal Integrity and Board Design for Xilinx FPGAs
  • Designing with Xilinx Serial Transceivers
  • Designing with UltraScale FPGA Transceivers
Updated at: 2016-01-13 16:09:20 +0100to the top
 
Questions or problems? support@so-logic.netWKO Impressum, Privacy and Policy