Admin >>
Customer login
  • so-logic
  • sozius
  • Activities
  • Knowledgebase
  • Trainings
  • IP Cores
  • Customers
  • Sitemap

Trainings

  • Search
  • Schedule
  • In-house Training
  • Create attendant account
  • AMD Xilinx
    • AI
    • Architecture
      • Versal
        • Designing with the Versal Adaptive SoC: Architecture
        • Designing with the Versal Adaptive SoC: Design Methodology
        • Designing with the Versal Adaptive SoC: Power and Board Design
        • Designing with the Versal Adaptive SoC: Memory Interfaces
        • Designing with the Versal Adaptive SoC: Hardware Debug
      • Designing with the UltraScale and UltraScale+ Architectures
      • Designing with AMD Xilinx 7 Series Families
      • Legacy
      • Versal Live Online Workshop Compendium Complete
    • Connectivity
    • DSP
    • Embedded
    • Languages
    • Tools
  • Doulos
  • Mathworks
  • National Instruments
  • so-logic
  • Payment conditions
  • Shopping Cart
  • Instruction

Versal

Courses

  • Designing with the Versal Adaptive SoC: Architecture
  • Designing with the Versal Adaptive SoC: Design Methodology
  • Designing with the Versal Adaptive SoC: Power and Board Design
  • Designing with the Versal Adaptive SoC: Memory Interfaces
  • Designing with the Versal Adaptive SoC: Hardware Debug
Updated at: 2024-10-31 17:00:37 +0100to the top
 
Questions or problems? support@so-logic.netWKO Impressum, Privacy and Policy