Admin >>
Sologo mainCustomer login
  • so-logic
  • sozius
  • Activities
  • Knowledgebase
  • Trainings
  • IP Cores
  • Customers
  • Sitemap

Trainings

  • RFSoc and Yocto for FPGA
  • Designing FPGAs with Xilinx Vivado Tools
  • soopendays 2012
  • Search
  • Schedule
  • In-house Training
  • Create attendant account
  • Doulos
  • Mathworks
  • National Instruments
  • so-logic
  • Xilinx
    • Architecture
      • Designing with the Zynq UltraScale+ RFSoC
      • Zynq SoC System Architecture
      • Designing with the UltraScale and UltraScale+ Architectures
      • Designing with Xilinx 7 Series Families
      • Designing with Spartan-6 and Virtex-6 Families
      • Designing with Virtex-5 FPGA Family
    • Connectivity
    • DSP
    • Embedded
    • Languages
    • Tools
  • Payment conditions
  • Shopping Cart
  • Instruction
Xilinx atp logo
Promo soziusnew
Promo pic1
Promo pic2
Promo pic3
Promo systemc

Architecture

En

Courses

  • Designing with the Zynq UltraScale+ RFSoC
  • Zynq SoC System Architecture
  • Designing with the UltraScale and UltraScale+ Architectures
  • Designing with Xilinx 7 Series Families
  • Designing with Spartan-6 and Virtex-6 Families
  • Designing with Virtex-5 FPGA Family
Updated at: 2009-12-04 13:45to the top
 
Questions or problems? support@so-logic.netWKO Impressum, Privacy and Policy