Design Compendium Verification for AMD Xilinx devices

Course Description

"Basic Functional Verification Tutorial" is a document made for beginners who are entering the world of verification. This tutorial explains, step by step, the procedure of different strategies of testing, discussing how the verification environment is structured and how the verification components interact with one another, as well as how the verification team has affects the testing strategy.

In the "Basic Functional Verification Tutorial", a hardware system that generates a PWM signal modulated using the sine wave with two different frequencies (1 Hz and 3.5Hz) will be tested. The hardware system used in this tutorial was generated in the "Basic FPGA Tutorial".

Release Date

July 2022

Training Duration

5 days

Purpose of this Tutorial

This tutorial is made to introduce you how to create a test bench file that stimulates the design with input patterns and calculates the expected responses for the output based of those input patterns.

The following project is designed for:

  • Designing Surface: VIVADO 2022.2
  • Programming Language: VHDL
  • Device: Sozius Development Board

After completing this tutorial, you will be able to:

  • guarantee that the design system has the desired functionality
  • find and localize hidden errors (bugs) present in the design
  • find all the bugs present in the design
  • know when the process of finding bugs is over
  • efficient implement the process of finding bugs

Lab Descriptions

  • Lab 1: "Introduction"
  • Lab 2: "Hardware Verification"
  • Lab 3: "Basic verification Environment"
  • Lab 4: "Step 1: Creating Stimulus Generator"
  • Lab 5: "Step 2: Creating Monitor"
  • Lab 6: "Step 3: Creating Checker and Scoreboard"
  • Lab 7: "Stimulus Definition File"
  • Lab 8: "Step 4: Creating PWM Checker"
  • Lab 9: "Step 5: Creating End-of-Test Checker"
  • Lab 10: "Creating a Random Stimulus Generation Test Bench"
  • Lab 11: "Measuring Verification Coverage"
  • Lab 12: "Regression Testing"
  • Lab 13: "Testbench Logging"
  • Lab 14: "VUnit Verification Components"
  • Lab 15: "OSVVM"
  • Lab 16: "Creating Deterministic Tests using OSVVM"

Event Schedule

so-logic (top1) (Austria)
  • 01.07. - 05.07.2024 09:00-17:00 — € 4,000.00 excl. VAT Add to cart
  • 09.09. - 13.09.2024 09:00-17:00 — € 4,000.00 excl. VAT Add to cart
  • 04.11. - 08.11.2024 09:00-17:00 — € 4,000.00 excl. VAT Add to cart


Updated at: 2024-03-07 14:32:55 +0100to the top