AES Core

Index

General Description
Features
Supported FPGA Families and Development Tools
Applications
Deliverables
Licensing
Documentation
Reference Design and Evaluation Version
Pricing and Additional Information

General Description

So-Logic's AES core uses the Advanced Encryption Standard with a 256-bit key (AES-256) as standardized in FIPS-197 in 2001 to provide confidentiality.

The AES-256 implementation used for Socius secure can operate at 1 gigabit per second in full-duplex mode at a minimum latency.

One big advantage of our FPGA based solution is that the AES-256 implementation can easily be replaced by any other algorithm, if the AES-256 gets broken.

The so_aes_ip core can be evaluated using Xilinx Evaluation Platforms before actual purchase. This is achieved by using a demonstration bit files for KC705 platform that allows the user to connect the So-Logic's complete 10G Ethernet solution system to some other Ethernet enabled device (PC or some Ethernet tester equipment) and evaluate system performance under different transfer scenarios.

For more information about the AES core please consult the corresponding user manual.

Features

• AES-128, AES-192, AES-256 GCM encryption
• Rounds are implemented sequential to reduce resources or concurrent to increase throughput
• AXI Streaming Interface with 8 bits or 128 bits wide depending of necessary speed
• Data confidentiality, integrity, and authenticity
• 1 Gbs and 10Gbs full duplex mode
• Simple usage, deployment, and administration
• Open platform allowing customization and verification
• Encryption algorithm can easily be modified or replaced

Supported FPGA Families and Development Tools

AES core currently supports following Xilinx FPGA device familes:

• Zynq-7000
• Artix-7
• Kintex-7
• Virtex-7
• Virtex-6
• Spartan-6
• Virtex-5

AES core currently supports following Xilinx development tools:

• Xilinx Vivado Design Suite

Applications

• LAN networking
• Industrial Ethernet
• Distributed Storage Area Networks
• Cloud computing

Deliverables

Source code (source code license only)

• VHDL Source Code

VHDL verification environment

• Tests with reference responses

Technical documentation

• Datasheet
• Installation notes
• User manual

Instantiation templates

Example application

Technical support

• IP Core implementation support
• Variable length maintenance
• Delivery of IP Core updates, minor and major changes
• Delivery of documentation updates
• Telephone & email support

Licensing

Netlist License

• Post-synthesis netlist
• Self checking testbench
• Test vectors for testing the core
• Place&Route scripts
• Constraints
• Instantiation templates
• Documentation

VHDL Source License

• VHDL RTL source code
• Complete verication plan together with the functional verication environment to verify the correct operation of the core
• Self checking testbench
• Vectors for testing the functionality of the core
• Simulation & synthesis scripts
• Documentation

Documentation

User Manual

For more information about the So-Logic AES core, please see the following user manual:

• AES core User Manual

Reference Design and Evaluation Version

Reference design as well as evaluation netlist are available for the AES core upon the request.

Reference design comes in a form of bit file for Zynq-7000, Artix-7, Kintex-7, Virtex-7, Virtex-6, Spartan-6 and Virtex-5 Xilinx FPGA Evaluation Platforms. Using this reference design, customer can connect it's Ethernet enabled device (network analyzer or PC) to the AES core and evaluate the functionality and performance of the core.

Evaluation netlists are also available upon a request. Using evaluation netlist user can integrate AES core into its specific application-related design and evaluate AES core performance in the target application for a limited period of time.

For more information about the reference design, please contact So-Logic at ip_ethernet@so-logic.net.

Pricing and Additional Information

Pricing of AES core varies, and is dependent on the license type. For information about the pricing, license types, additional documents, performance, example applications, or any other information regarding the AES core, please contact So-Logic at:

Phone: +43-1-315 77 77-11
Fax: +43-1-315 77 77-44
email: ip_ethernet@so-logic.net