Design Compendium High Level Synthesis for AMD Xilinx devices

Course Description

"Basic HLS Tutorial" is a document made for beginners who are entering the world of embedded system design using FPGAs.This tutorial explains, step by step, the procedure of designing a simple digital system using C/C++/SystemC languages and AMD Xilinx Vivado Design Suite.

In the "Basic HLS Tutorial", a PWM signal modulated using the sine wave with two different frequencies (1 Hz and 3.5Hz) will be created. Frequency that will be chosen depends on the position of the two-state on-board switch.

Training Duration

5 days

Purpose of this Tutorial

This tutorial is made to introduce you how to create, simulate and test an project and run it on your development board.

The following project is designed for:

  • Designing Surface: VIVADO 2022.2
  • Programming Language: C
  • Device: Sozius Development Board

After completing this tutorial, you will be able to:

  • Launch and navigate the Vivado High-Level Synthesis (HLS) tool
  • Create a project using New Project Creation Wizard
  • Develop a C algorithm for your design
  • Verify a C algorithm of your design
  • Synthesize a C algorithm into an RTL implementation (High-Level Synthesis)
  • Generate reports and analyze the design
  • Verify the RTL implementation
  • Package the RTL implementations
  • Introduction to High-Level Synthesis and the Vivado HLS Tool
  • Using the Vivado HLS Tool: GUI Flow
  • Demo: Vivado HLS Tool Overview
  • Lab 1: Introduction to the Vivado HLS Tool Flow
  • Lab 2: Introduction to the Vivado HLS CLI Flow
  • I/O Interface
  • Demo: AXI-4 Stream Interfaces
  • Lab 3: Interface Synthesis
  • Pipelining for Performance
  • Demo: Pipelining for Performance
  • Lab 4: Improving Performance
  • Optimizing Structures for Performance
  • Demo: Handling Memories
  • Lab 5: Implementing Arrays as RTL Interfaces
  • Reducing Latency
  • Improving Area
  • Lab 6: Improving Area and Resource Utilization
  • Introduction to the HLx Design Flow
  • Demo: Using Vivado HLS IP with SysGen
  • Lab 7: HLx Flow - System Generation
  • HLS vs. Vits Environment Flow

Lab Descriptions

  • Lab 1: "Introduction"
  • Lab 2: "About HLS Tool"
  • Lab 3: "Developing Custom IP Core using HLS"
  • Lab 4: "Using Developed IP Core in Vivado Design Suite"
  • Lab 5: "Design an FIR filter
  • Lab 6: "Design an DCT
  • Lab 7: "Design an AES encryption
  • Lab 8: "Design an YOUR IP

Event Schedule

so-logic (top1) (Austria)
  • 22.07. - 25.07.2024 09:00-17:00 — € 4,000.00 excl. VAT Add to cart
  • 23.09. - 27.09.2024 09:00-17:00 — € 4,000.00 excl. VAT Add to cart
  • 25.11. - 29.11.2024 09:00-17:00 — € 4,000.00 excl. VAT Add to cart


Updated at: 2024-03-07 12:27:32 +0100to the top