Designing FPGAs Using the Vivado Design Suite 4
Learn how to use the advanced aspects of the Vivado™ Design Suite.
The focus is on:
Applying techniques to reduce delay and to improve clock skew and clock uncertainty
Utilizing floorplanning techniques
Employing advanced implementation options
Utilizing AMD security features
Identifying advanced FPGA configurations
Debugging a design at the device startup phase
Utilizing Tcl scripting when using the Vivado logic analyzer in a design
Event Schedule
Virtual Learning Environment (Online)
- 16.10. - 17.10.2025 09:00-17:00 — € 1,700.00 excl. VAT Add to cart
- 17.07. - 18.07.2025 09:00-17:00 — € 1,700.00 excl. VAT Add to cart
- 17.04. - 18.04.2025 09:00-17:00 — € 1,700.00 excl. VAT Add to cart