Decision Tree Ensemble Inference Core

Index

General Description
Features
Applications
Deliverables
Licensing
Datasheet
Reference Design
Pricing and Additional Information

General Description

So_ip_idte core can be used create an ensemble of decision trees directly in hardware. DTs that make up the ensemble can have univarite, multivariate and non-linear tests. Creating DT ensemble directly in hardware results in the significant increase of the inference speed, compared with the traditional software-based approach.

So_ip_idte core uses bagging algorithm to create a DT ensemble.

Bagging is one of the earliest proposed ensemble-creation algorithms. It is also one of the most intuitive and simplest to implement, with surprisingly good performance. Bagging is particularly appealing when the available data is of limited size. Bagging algorithm can be easily parallelized in contrast to most other popular methods for the ensemble classifier creation. At the hart of the bagging algorithm a proprietary DT inference algorithm based on the evolutionary algorithms, developed at So-Logic, is used to infer individual DT members in parallel. This approach results in very fast DT ensemble inference times while still having acceptable resource requirements.

After the inference process is complete, complete structural information about the created DTs is transferred through the output ports. This information can be easily transferred to some of the So-Logic’s DT ensemble evaluation cores enabling hardware implementation of the inferred DT ensemble. By combining these two cores a hardware-based adaptive learning ensemble systems can be easily designed.

So_ip_idte core is delivered with fully automated testbench and a compete set of tests allowing easy package validation at each stage of SoC design flow.

The so_ip_idte design is strictly synchronous with positive-edge clocking, no internal tri-states and a synchronous reset.

The so_ip_idte core can be evaluated using any evaluation platform available to the user before actual purchase. This is achieved by using a time-limited demonstration bit files for selected platform that allows the user to evaluate system performance under different usage scenarios.

For more information about the so_ip_idte core please consult the corresponding datasheet.

Features

  • Enables DT ensemble creation directly in hardware
  • Speedup of inference time of over 1000x compared to the traditional software approach
  • Supports classification problems that are defined by numerical attributes only
  • DTs with univariate or multivariate tests are supported
  • DTs with nonlinear tests are supported
  • No special IP blocks are needed to implement the core, only memory, adders and multipliers
  • User can specify the number format for all DT ensemble parameters in order to achieve the best performance/size ratio after implementation
  • Can be easily integrated with some of the So-Logic’s DT ensemble evaluation cores to create hardware-based adaptive learning ensemble systems

Applications

  • Speech and handwriting recognition
  • Computer vision
  • Machine perception
  • Pattern recognition
  • Medical diagnosis
  • Robot locomotion
  • Adaptive systems

    • Deliverables

    Source code (source code license only)

    • VHDL Source Code

    VHDL verification environment

    • Tests with reference responses

    Technical documentation

    • Installation notes
    • HDL core specification
    • Datasheet

    Instantiation templates

    Reference design

    Technical support

    • IP Core implementation support
    • Variable length maintenance
    • Delivery of IP Core updates, minor and major changes
    • Delivery of documentation updates
    • Telephone & email support

    Licensing

    Netlist License

    • Post-synthesis netlist
    • Self checking testbench
    • Test vectors for testing the core
    • Place&Route scripts
    • Constraints
    • Instantiation templates
    • Documentation

    VHDL Source License

    • VHDL RTL source code
    • Complete verification plan together with testbenches needed to verify correct operation of the core
    • Self checking testbench
    • Vectors for testing the functionality of the core
    • Simulation & synthesis scripts
    • Documentation

    Datasheet

    For more information about the So-Logic decision tree ensemble inference core, please see the following datasheet:

    Reference Design

    Reference design for the so_ip_idte decision tree ensemble inference core is avaiable upon the request. Reference design comes in a form of bit file for user specified platform. Using this reference design, customer can evaluate the functionality and performance of the core for limited period of time. For more information about the reference design, please contact So-Logic at ip_idte@so-logic.net.

    Pricing and Additional Information

    Pricing of so_ip_idte decision tree ensemble inference core varies, and is dependent on the license type. For information about the pricing, license types, additional documents, performance, example applications, or any other information regarding the so_ip_idte decision tree ensemble inference core, please contact So-Logic at:

    Phone: +43-1-315 77 77-11
    Fax:     +43-1-315 77 77-44
    email:  ip_idte@so-logic.net

Updated at: 2011-01-15 22:22:15 +0100to the top