|
27.01. - 27.01.2020 09:00-17:00
|
Designing with Verilog
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 750.00
|
Add to cart
|
|
27.01. - 29.01.2020 09:00-17:00
|
Designing with VHDL
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 2,250.00
|
Add to cart
|
|
28.01. - 29.01.2020 09:00-17:00
|
Designing with System Verilog
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 1,500.00
|
Add to cart
|
|
30.01. - 31.01.2020 09:00-17:00
|
Verification with System Verilog
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 1,500.00
|
Add to cart
|
|
30.01. - 31.01.2020 09:00-17:00
|
Advanced VHDL
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 1,500.00
|
Add to cart
|
|
03.02. - 04.02.2020 09:00-17:00
|
Zynq UltraScale+ MPSoC for the System Architect
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 1,500.00
|
Add to cart
|
|
05.02. - 06.02.2020 09:00-17:00
|
Embedded Systems Software Design
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 1,500.00
|
Add to cart
|
|
05.02. - 06.02.2020 09:00-17:00
|
Zynq UltraScale+ MPSoC for the Software Developer
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 1,500.00
|
Add to cart
|
|
06.02. - 07.02.2020 09:00-17:00
|
Zynq All Programmable SoC System Architecture
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 1,500.00
|
Add to cart
|
|
07.02. - 07.02.2020 09:00-17:00
|
Advanced Features and Techniques of Embedded Systems Software Design
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 750.00
|
Add to cart
|
|
07.02. - 07.02.2020 09:00-17:00
|
Zynq UltraScale+ MPSoC for the Hardware Designer
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 750.00
|
Add to cart
|
|
10.02. - 12.02.2020 09:00-17:00
|
Designing with Multi-Gigabit Serial I/O
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 2,250.00
|
Add to cart
|
|
10.02. - 11.02.2020 09:00-17:00
|
Designing with Ethernet MAC Controllers
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 1,500.00
|
Add to cart
|
|
12.02. - 13.02.2020 09:00-17:00
|
Designing with UltraScale FPGA Transceivers
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 1,500.00
|
Add to cart
|
|
12.02. - 13.02.2020 09:00-17:00
|
Designing a LogiCORE PCI Express System
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 1,500.00
|
Add to cart
|
|
17.02. - 19.02.2020 09:00-17:00
|
Designing FPGAs Using the Vivado Design Suite 1
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 1,500.00
|
Add to cart
|
|
19.02. - 20.02.2020 09:00-17:00
|
Designing FPGAs Using the Vivado Design Suite 2
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 1,500.00
|
Add to cart
|
|
02.03. - 04.03.2020 09:00-17:00
|
Designing FPGAs Using the Vivado Design Suite 3
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 1,500.00
|
Add to cart
|
|
04.03. - 04.03.2020 09:00-17:00
|
Designing FPGAs Using the Vivado Design Suite 4
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 750.00
|
Add to cart
|
|
05.03. - 06.03.2020 09:00-17:00
|
Partial Reconfiguration
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 1,500.00
|
Add to cart
|
|
16.03. - 17.03.2020 09:00-17:00
|
C-based Design: High-Level Synthesis with Vivado HLS
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 1,500.00
|
Add to cart
|
|
20.03. - 20.03.2020 09:00-17:00
|
Developing AWS F1 Applications Using the SDAccel Environment
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 750.00
|
Add to cart
|
|
23.03. - 24.03.2020 09:00-17:00
|
Essential DSP Implementation Techniques for Xilinx FPGAs
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 1,500.00
|
Add to cart
|
|
26.03. - 27.03.2020 09:00-17:00
|
DSP Design Using System Generator
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 1,500.00
|
Add to cart
|
|
30.03. - 01.04.2020 09:00-17:00
|
Designing with VHDL
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 2,250.00
|
Add to cart
|
|
30.03. - 30.03.2020 09:00-17:00
|
Designing with Verilog
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 1,500.00
|
Add to cart
|
|
31.03. - 31.03.2020 09:00-17:00
|
Designing with System Verilog
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 1,500.00
|
Add to cart
|
|
02.04. - 03.04.2020 09:00-17:00
|
Verification with System Verilog
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 1,500.00
|
Add to cart
|
|
02.04. - 03.04.2020 09:00-17:00
|
Advanced VHDL
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 1,500.00
|
Add to cart
|
|
06.04. - 07.04.2020 09:00-17:00
|
Zynq UltraScale+ MPSoC for the System Architect
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 1,500.00
|
Add to cart
|
|
07.04. - 08.04.2020 09:00-17:00
|
Designing with the Zynq UltraScale+ RFSoC
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 1,500.00
|
Add to cart
|
|
08.04. - 09.04.2020 09:00-17:00
|
Zynq UltraScale+ MPSoC for the Software Developer
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 1,500.00
|
Add to cart
|
|
08.04. - 09.04.2020 09:00-17:00
|
Advanced Features and Techniques of Embedded Systems Software Design
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 1,500.00
|
Add to cart
|
|
14.04. - 15.04.2020 09:00-17:00
|
Designing with Ethernet MAC Controllers
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 1,500.00
|
Add to cart
|
|
14.04. - 14.04.2020 09:00-17:00
|
Zynq UltraScale+ MPSoC for the Hardware Designer
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 750.00
|
Add to cart
|
|
14.04. - 14.04.2020 09:00-17:00
|
Advanced Features and Techniques of Embedded Systems Software Design
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 750.00
|
Add to cart
|
|
14.04. - 16.04.2020 09:00-17:00
|
Designing with Multi-Gigabit Serial I/O
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 2,250.00
|
Add to cart
|
|
16.04. - 17.04.2020 09:00-17:00
|
Zynq All Programmable SoC System Architecture
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 1,500.00
|
Add to cart
|
|
20.04. - 21.04.2020 09:00-17:00
|
Designing a LogiCORE PCI Express System
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 1,500.00
|
Add to cart
|
|
20.04. - 21.04.2020 09:00-17:00
|
Designing with UltraScale FPGA Transceivers
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 1,500.00
|
Add to cart
|
|
27.04. - 28.04.2020 09:00-17:00
|
Designing FPGAs Using the Vivado Design Suite 1
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 1,500.00
|
Add to cart
|
|
29.04. - 30.04.2020 09:00-17:00
|
Designing FPGAs Using the Vivado Design Suite 2
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 1,500.00
|
Add to cart
|
|
05.05. - 06.05.2020 09:00-17:00
|
Designing FPGAs Using the Vivado Design Suite 3
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 1,500.00
|
Add to cart
|
|
07.05. - 08.05.2020 09:00-17:00
|
Partial Reconfiguration
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 1,500.00
|
Add to cart
|
|
11.05. - 12.05.2020 09:00-17:00
|
C-based Design: High-Level Synthesis with Vivado HLS
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 1,500.00
|
Add to cart
|
|
11.05. - 11.05.2020 09:00-17:00
|
Designing FPGAs Using the Vivado Design Suite 4
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 750.00
|
Add to cart
|
|
15.05. - 15.05.2020 09:00-17:00
|
Developing AWS F1 Applications Using the SDAccel Environment
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 750.00
|
Add to cart
|
|
19.05. - 19.05.2020 09:00-17:00
|
Essential DSP Implementation Techniques for Xilinx FPGAs
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 1,500.00
|
Add to cart
|
|
25.05. - 27.05.2020 09:00-17:00
|
Designing with VHDL
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 2,250.00
|
Add to cart
|
|
25.05. - 26.05.2020 09:00-17:00
|
DSP Design Using System Generator
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 1,500.00
|
Add to cart
|
|
25.05. - 25.05.2020 09:00-17:00
|
Designing with Verilog
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 750.00
|
Add to cart
|
|
26.05. - 27.05.2020 09:00-17:00
|
Designing with System Verilog
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 1,500.00
|
Add to cart
|
|
28.05. - 29.05.2020 09:00-17:00
|
Advanced VHDL
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 1,500.00
|
Add to cart
|
|
28.05. - 29.05.2020 09:00-17:00
|
Verification with System Verilog
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 1,500.00
|
Add to cart
|
|
15.06. - 16.06.2020 09:00-17:00
|
Zynq UltraScale+ MPSoC for the System Architect
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 1,500.00
|
Add to cart
|
|
16.06. - 17.06.2020 09:00-17:00
|
Zynq All Programmable SoC System Architecture
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 1,500.00
|
Add to cart
|
|
17.06. - 18.06.2020 09:00-17:00
|
Zynq UltraScale+ MPSoC for the Software Developer
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 1,500.00
|
Add to cart
|
|
17.06. - 18.06.2020 09:00-17:00
|
Embedded Systems Software Design
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 1,500.00
|
Add to cart
|
|
18.06. - 19.06.2020 09:00-17:00
|
Designing with the Zynq UltraScale+ RFSoC
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 1,500.00
|
Add to cart
|
|
19.06. - 19.06.2020 09:00-17:00
|
Advanced Features and Techniques of Embedded Systems Software Design
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 750.00
|
Add to cart
|
|
19.06. - 19.06.2020 09:00-17:00
|
Zynq UltraScale+ MPSoC for the Hardware Designer
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 750.00
|
Add to cart
|
|
22.06. - 24.06.2020 09:00-17:00
|
Designing with Multi-Gigabit Serial I/O
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 2,250.00
|
Add to cart
|
|
22.06. - 23.06.2020 09:00-17:00
|
Designing with Ethernet MAC Controllers
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 1,500.00
|
Add to cart
|
|
24.06. - 25.06.2020 09:00-17:00
|
Designing with UltraScale FPGA Transceivers
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 1,500.00
|
Add to cart
|
|
24.06. - 25.06.2020 09:00-17:00
|
Designing a LogiCORE PCI Express System
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 1,500.00
|
Add to cart
|
|
29.06. - 30.06.2020 09:00-17:00
|
Designing FPGAs Using the Vivado Design Suite 1
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 1,500.00
|
Add to cart
|
|
01.07. - 02.07.2020 09:00-17:00
|
Designing FPGAs Using the Vivado Design Suite 2
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 1,500.00
|
Add to cart
|
|
06.07. - 07.07.2020 09:00-17:00
|
Designing FPGAs Using the Vivado Design Suite 3
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 1,500.00
|
Add to cart
|
|
08.07. - 08.07.2020 09:00-17:00
|
Designing FPGAs Using the Vivado Design Suite 4
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 750.00
|
Add to cart
|
|
09.07. - 10.07.2020 09:00-17:00
|
Partial Reconfiguration
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 1,500.00
|
Add to cart
|
|
20.07. - 21.07.2020 09:00-17:00
|
C-based Design: High-Level Synthesis with Vivado HLS
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 1,500.00
|
Add to cart
|
|
24.07. - 24.07.2020 09:00-17:00
|
Developing AWS F1 Applications Using the SDAccel Environment
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 750.00
|
Add to cart
|
|
27.07. - 28.07.2020 09:00-17:00
|
Essential DSP Implementation Techniques for Xilinx FPGAs
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 1,500.00
|
Add to cart
|
|
29.07. - 30.07.2020 09:00-17:00
|
DSP Design Using System Generator
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 1,500.00
|
Add to cart
|
|
03.08. - 05.08.2020 09:00-17:00
|
Designing with VHDL
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 2,250.00
|
Add to cart
|
|
03.08. - 03.08.2020 09:00-17:00
|
Designing with Verilog
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 750.00
|
Add to cart
|
|
04.08. - 06.08.2020 09:00-17:00
|
Verification with System Verilog
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 1,500.00
|
Add to cart
|
|
06.08. - 07.08.2020 09:00-17:00
|
Advanced VHDL
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 1,500.00
|
Add to cart
|
|
06.08. - 07.08.2020 09:00-17:00
|
Verification with System Verilog
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 1,500.00
|
Add to cart
|
|
10.08. - 11.08.2020 09:00-17:00
|
Zynq UltraScale+ MPSoC for the System Architect
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 1,500.00
|
Add to cart
|
|
11.08. - 12.08.2020 09:00-17:00
|
Zynq All Programmable SoC System Architecture
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 1,500.00
|
Add to cart
|
|
12.08. - 13.08.2020 09:00-17:00
|
Zynq UltraScale+ MPSoC for the Software Developer
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 1,500.00
|
Add to cart
|
|
12.08. - 13.08.2020 09:00-17:00
|
Embedded Systems Software Design
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 1,500.00
|
Add to cart
|
|
13.08. - 14.08.2020 09:00-17:00
|
Designing with the Zynq UltraScale+ RFSoC
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 1,500.00
|
Add to cart
|
|
14.08. - 14.08.2020 09:00-17:00
|
Advanced Features and Techniques of Embedded Systems Software Design
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 750.00
|
Add to cart
|
|
14.08. - 14.08.2020 09:00-17:00
|
Zynq UltraScale+ MPSoC for the Hardware Designer
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 750.00
|
Add to cart
|
|
17.08. - 18.08.2020 09:00-17:00
|
Designing with Ethernet MAC Controllers
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 1,500.00
|
Add to cart
|
|
17.08. - 19.08.2020 09:00-17:00
|
Designing with Multi-Gigabit Serial I/O
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 2,250.00
|
Add to cart
|
|
19.08. - 20.08.2020 09:00-17:00
|
Designing with UltraScale FPGA Transceivers
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 1,500.00
|
Add to cart
|
|
20.08. - 21.08.2020 09:00-17:00
|
Designing a LogiCORE PCI Express System
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 1,500.00
|
Add to cart
|
|
24.08. - 25.08.2020 09:00-17:00
|
Designing FPGAs Using the Vivado Design Suite 1
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 1,500.00
|
Add to cart
|
|
26.08. - 27.08.2020 09:00-17:00
|
Designing FPGAs Using the Vivado Design Suite 2
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 1,500.00
|
Add to cart
|
|
31.08. - 01.09.2020 09:00-17:00
|
Designing FPGAs Using the Vivado Design Suite 3
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 1,500.00
|
Add to cart
|
|
02.09. - 02.09.2020 09:00-17:00
|
Designing FPGAs Using the Vivado Design Suite 4
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 750.00
|
Add to cart
|
|
03.09. - 04.09.2020 09:00-17:00
|
Partial Reconfiguration
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 1,500.00
|
Add to cart
|
|
14.09. - 15.09.2020 09:00-17:00
|
C-based Design: High-Level Synthesis with Vivado HLS
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 1,500.00
|
Add to cart
|
|
18.09. - 18.09.2020 09:00-17:00
|
Developing AWS F1 Applications Using the SDAccel Environment
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 750.00
|
Add to cart
|
|
28.09. - 29.09.2020 09:00-17:00
|
Essential DSP Implementation Techniques for Xilinx FPGAs
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 1,500.00
|
Add to cart
|
|
01.10. - 02.10.2020 09:00-17:00
|
DSP Design Using System Generator
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 1,500.00
|
Add to cart
|
|
05.10. - 07.10.2020 09:00-17:00
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Designing with VHDL
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 2,250.00
|
Add to cart
|
|
05.10. - 05.10.2020 09:00-17:00
|
Designing with Verilog
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 750.00
|
Add to cart
|
|
06.10. - 07.10.2020 09:00-17:00
|
Designing with System Verilog
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 1,500.00
|
Add to cart
|
|
08.10. - 09.10.2020 09:00-17:00
|
Verification with System Verilog
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 1,500.00
|
Add to cart
|
|
08.10. - 09.10.2020 09:00-17:00
|
Advanced VHDL
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 1,500.00
|
Add to cart
|
|
12.10. - 13.10.2020 09:00-17:00
|
Zynq UltraScale+ MPSoC for the System Architect
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 1,500.00
|
Add to cart
|
|
13.10. - 14.10.2020 09:00-17:00
|
Zynq All Programmable SoC System Architecture
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 1,500.00
|
Add to cart
|
|
14.10. - 15.10.2020 09:00-17:00
|
Embedded Systems Software Design
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 1,500.00
|
Add to cart
|
|
14.10. - 15.10.2020 09:00-17:00
|
Zynq UltraScale+ MPSoC for the Software Developer
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 1,500.00
|
Add to cart
|
|
15.10. - 16.10.2020 09:00-17:00
|
Designing with the Zynq UltraScale+ RFSoC
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 1,500.00
|
Add to cart
|
|
16.10. - 16.10.2020 09:00-17:00
|
Zynq UltraScale+ MPSoC for the Hardware Designer
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 750.00
|
Add to cart
|
|
16.10. - 16.10.2020 09:00-17:00
|
Advanced Features and Techniques of Embedded Systems Software Design
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 750.00
|
Add to cart
|
|
19.10. - 20.10.2020 09:00-17:00
|
Designing with Ethernet MAC Controllers
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 1,500.00
|
Add to cart
|
|
19.10. - 21.10.2020 09:00-17:00
|
Designing with Multi-Gigabit Serial I/O
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 2,250.00
|
Add to cart
|
|
22.10. - 23.10.2020 09:00-17:00
|
Designing with UltraScale FPGA Transceivers
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 1,500.00
|
Add to cart
|
|
22.10. - 23.10.2020 09:00-17:00
|
Designing a LogiCORE PCI Express System
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 1,500.00
|
Add to cart
|
|
27.10. - 28.10.2020 09:00-17:00
|
Designing FPGAs Using the Vivado Design Suite 1
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 1,500.00
|
Add to cart
|
|
29.10. - 30.10.2020 09:00-17:00
|
Designing FPGAs Using the Vivado Design Suite 2
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 1,500.00
|
Add to cart
|
|
03.11. - 04.11.2020 09:00-17:00
|
Designing FPGAs Using the Vivado Design Suite 3
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 1,500.00
|
Add to cart
|
|
05.11. - 05.11.2020 09:00-17:00
|
Designing FPGAs Using the Vivado Design Suite 4
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 750.00
|
Add to cart
|
|
09.11. - 10.11.2020 09:00-17:00
|
Partial Reconfiguration
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 1,500.00
|
Add to cart
|
|
23.11. - 24.11.2020 09:00-17:00
|
C-based Design: High-Level Synthesis with Vivado HLS
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 1,500.00
|
Add to cart
|
|
27.11. - 27.11.2020 09:00-17:00
|
Developing AWS F1 Applications Using the SDAccel Environment
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 750.00
|
Add to cart
|
|
30.11. - 01.12.2020 09:00-17:00
|
Essential DSP Implementation Techniques for Xilinx FPGAs
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 1,500.00
|
Add to cart
|
|
02.12. - 03.12.2020 09:00-17:00
|
DSP Design Using System Generator
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 1,500.00
|
Add to cart
|
|
14.12. - 14.12.2020 09:00-17:00
|
Designing with Verilog
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 750.00
|
Add to cart
|
|
14.12. - 16.12.2020 09:00-17:00
|
Designing with VHDL
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 2,250.00
|
Add to cart
|
|
16.12. - 18.12.2020 09:00-17:00
|
Designing with System Verilog
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 1,500.00
|
Add to cart
|
|
17.12. - 18.12.2020 09:00-17:00
|
Advanced VHDL
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 1,500.00
|
Add to cart
|
|
17.12. - 18.12.2020 09:00-17:00
|
Verification with System Verilog
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 1,500.00
|
Add to cart
|
