Training schedules 2024-03-19 - 2025-03-19
Event period | Training | Partner | Location | Price | |
---|---|---|---|---|---|
22.03. - 22.03.2024 09:00-17:00 | Designing with the Versal ACAP: Network on Chip | Xilinx | so-logic (top1) (Austria) | € 800.00 | |
25.03. - 26.03.2024 09:00-17:00 | Zynq UltraScale+ MPSoC for the System Architect | Xilinx | so-logic (top1) (Austria) | € 1,600.00 | |
25.03. - 29.03.2024 09:00-17:00 | Design Compendium with High Level Synthesis for AMX Xilinx devices | so-logic | so-logic (top1) (Austria) | € 4,000.00 | |
27.03. - 28.03.2024 09:00-17:00 | Zynq UltraScale+ MPSoC for the Software Developer | Xilinx | so-logic (top1) (Austria) | € 1,600.00 | |
29.03. - 29.03.2024 09:00-17:00 | Zynq UltraScale+ MPSoC for the Hardware Designer | Xilinx | so-logic (top1) (Austria) | € 800.00 | |
01.04. - 05.04.2024 09:00-17:00 | Design Compendium with VHDL for AMD Xilinx devices | so-logic | so-logic (top1) (Austria) | € 4,000.00 | |
03.04. - 05.04.2024 09:00-17:00 | Designing with the UltraScale and UltraScale+ Architectures | Xilinx | so-logic (top1) (Austria) | € 2,400.00 | |
04.04. - 08.04.2024 09:00-17:00 | Design Compendium Embedded System for AMD XIlinx devices | so-logic | so-logic (top1) (Austria) | € 4,000.00 | |
08.04. - 09.04.2024 09:00-17:00 | Migrating to the Vitis Embedded Software Development IDE Workshop | Xilinx | so-logic (top1) (Austria) | € 1,600.00 | |
10.04. - 12.04.2024 09:00-17:00 | High-Level Synthesis with Vitis HLS | Xilinx | so-logic (top1) (Austria) | € 2,400.00 | |
15.04. - 15.04.2024 09:00-17:00 | AMD Versal Compendium 1 : Architecture | so-logic | so-logic (top1) (Austria) | € 0.00 | |
15.04. - 19.04.2024 09:00-17:00 | Design Compendium Yocto for AMD Xilinx devices | so-logic | so-logic (top1) (Austria) | € 4,000.00 | |
15.04. - 16.04.2024 09:00-17:00 | Designing FPGAs Using the Vivado Design Suite 1 | Xilinx | so-logic (top1) (Austria) | € 1,600.00 | |
17.04. - 18.04.2024 09:00-17:00 | Designing FPGAs Using the Vivado Design Suite 2 | Xilinx | so-logic (top1) (Austria) | € 1,600.00 | |
21.04. - 22.04.2024 09:00-17:00 | Designing FPGAs Using the Vivado Design Suite 3 | Xilinx | so-logic (top1) (Austria) | € 1,600.00 | |
23.04. - 24.04.2024 09:00-17:00 | Designing FPGAs Using the Vivado Design Suite 4 | Xilinx | so-logic (top1) (Austria) | € 1,600.00 | |
28.04. - 30.04.2024 09:00-17:00 | Designing with VHDL | Xilinx | so-logic (top1) (Austria) | € 2,400.00 | |
01.05. - 02.05.2024 09:00-17:00 | Advanced VHDL | Xilinx | so-logic (top1) (Austria) | € 1,600.00 | |
05.05. - 07.05.2024 09:00-17:00 | Designing with Verilog | Xilinx | so-logic (top1) (Austria) | € 2,400.00 | |
05.05. - 09.05.2024 09:00-17:00 | Design Compendium with Verilog for AMD Xilinx devices | so-logic | so-logic (top1) (Austria) | € 4,000.00 | |
06.05. - 10.05.2024 09:00-17:00 | Design Compendium Verfication with VHDL for AMD Xilinx devices | so-logic | so-logic (top1) (Austria) | € 4,000.00 | |
08.05. - 09.05.2024 09:00-17:00 | Designing with SystemVerilog | Xilinx | so-logic (top1) (Austria) | € 1,600.00 | |
12.05. - 13.05.2024 09:00-17:00 | Verification with SystemVerilog | Xilinx | so-logic (top1) (Austria) | € 1,600.00 | |
14.05. - 15.05.2024 09:00-17:00 | Embedded Design with PetaLinux Tools | Xilinx | so-logic (top1) (Austria) | € 1,600.00 | |
20.05. - 24.05.2024 09:00-17:00 | Design Compendium with SystemC for AMD Xilinx devices | so-logic | so-logic (top1) (Austria) | € 4,000.00 | |
27.05. - 31.05.2024 09:00-17:00 | Design Compendium with High Level Synthesis for AMX Xilinx devices | so-logic | so-logic (top1) (Austria) | € 4,000.00 | |
03.06. - 04.06.2024 09:00-17:00 | Designing with Versal AI Engine 1 - Architecture and Design Flow | Xilinx | so-logic (top1) (Austria) | € 1,600.00 | |
05.06. - 07.06.2024 09:00-17:00 | Designing with Versal AI Engine 2: Graph Programming with AI Engine Kernels | Xilinx | so-logic (top1) (Austria) | € 2,400.00 | |
06.06. - 10.06.2024 09:00-17:00 | Design Compendium with VHDL for AMD Xilinx devices | so-logic | so-logic (top1) (Austria) | € 4,000.00 | |
06.06. - 10.06.2024 09:00-17:00 | Design Compendium Yocto for AMD Xilinx devices | so-logic | so-logic (top1) (Austria) | € 4,000.00 | |
10.06. - 12.06.2024 09:00-17:00 | Designing with Versal AI Engine 3: Kernel Programming and Optimization | Xilinx | so-logic (top1) (Austria) | € 2,400.00 | |
10.06. - 14.06.2024 09:00-17:00 | Design Compendium Embedded System for AMD XIlinx devices | so-logic | so-logic (top1) (Austria) | € 4,000.00 | |
13.06. - 14.06.2024 09:00-17:00 | Designing with the Versal ACAP: PCI Express Systems | Xilinx | so-logic (top1) (Austria) | € 1,600.00 | |
17.06. - 20.06.2024 09:00-17:00 | Designing with the Versal ACAP: Architecture and Methodology | Xilinx | so-logic (top1) (Austria) | € 3,200.00 | |
21.06. - 21.06.2024 09:00-17:00 | Designing with the Versal ACAP: Network on Chip | Xilinx | so-logic (top1) (Austria) | € 800.00 | |
24.06. - 25.06.2024 09:00-17:00 | Zynq UltraScale+ MPSoC for the System Architect | Xilinx | so-logic (top1) (Austria) | € 1,600.00 | |
26.06. - 27.06.2024 09:00-17:00 | Zynq UltraScale+ MPSoC for the Software Developer | Xilinx | so-logic (top1) (Austria) | € 1,600.00 | |
28.06. - 28.06.2024 09:00-17:00 | Zynq UltraScale+ MPSoC for the Hardware Designer | Xilinx | so-logic (top1) (Austria) | € 800.00 | |
01.07. - 05.07.2024 09:00-17:00 | Design Compendium Verfication with VHDL for AMD Xilinx devices | so-logic | so-logic (top1) (Austria) | € 4,000.00 | |
03.07. - 05.07.2024 09:00-17:00 | Designing with the UltraScale and UltraScale+ Architectures | Xilinx | so-logic (top1) (Austria) | € 2,400.00 | |
07.07. - 11.07.2024 09:00-17:00 | Design Compendium with SystemC for AMD Xilinx devices | so-logic | so-logic (top1) (Austria) | € 4,000.00 | |
08.07. - 12.07.2024 09:00-17:00 | Design Compendium with Verilog for AMD Xilinx devices | so-logic | so-logic (top1) (Austria) | € 4,000.00 | |
08.07. - 08.07.2024 09:00-17:00 | AMD Versal Compendium 2 : High Speed Communication | so-logic | so-logic (top1) (Austria) | € 0.00 | |
08.07. - 08.07.2024 09:00-17:00 | Migrating to the Vitis Embedded Software Development IDE Workshop | Xilinx | so-logic (top1) (Austria) | € 1,600.00 | |
10.07. - 12.07.2024 09:00-17:00 | High-Level Synthesis with Vitis HLS | Xilinx | so-logic (top1) (Austria) | € 2,400.00 | |
15.07. - 16.07.2024 09:00-17:00 | Designing FPGAs Using the Vivado Design Suite 1 | Xilinx | so-logic (top1) (Austria) | € 1,600.00 | |
17.07. - 18.07.2024 09:00-17:00 | Designing FPGAs Using the Vivado Design Suite 2 | Xilinx | so-logic (top1) (Austria) | € 1,600.00 | |
21.07. - 22.07.2024 09:00-17:00 | Designing FPGAs Using the Vivado Design Suite 3 | Xilinx | so-logic (top1) (Austria) | € 1,600.00 | |
22.07. - 25.07.2024 09:00-17:00 | Design Compendium with High Level Synthesis for AMX Xilinx devices | so-logic | so-logic (top1) (Austria) | € 4,000.00 | |
23.07. - 24.07.2024 09:00-17:00 | Designing FPGAs Using the Vivado Design Suite 4 | Xilinx | so-logic (top1) (Austria) | € 1,600.00 | |
28.07. - 30.07.2024 09:00-17:00 | Designing with VHDL | Xilinx | so-logic (top1) (Austria) | € 2,400.00 | |
29.07. - 02.08.2024 09:00-17:00 | Design Compendium with VHDL for AMD Xilinx devices | so-logic | so-logic (top1) (Austria) | € 4,000.00 | |
31.07. - 01.08.2024 09:00-17:00 | Advanced VHDL | Xilinx | so-logic (top1) (Austria) | € 1,600.00 | |
04.08. - 06.08.2024 09:00-17:00 | Designing with Verilog | Xilinx | so-logic (top1) (Austria) | € 2,400.00 | |
05.08. - 09.08.2024 09:00-17:00 | Design Compendium Embedded System for AMD XIlinx devices | so-logic | so-logic (top1) (Austria) | € 4,000.00 | |
07.08. - 08.08.2024 09:00-17:00 | Designing with SystemVerilog | Xilinx | so-logic (top1) (Austria) | € 1,600.00 | |
11.08. - 12.08.2024 09:00-17:00 | Verification with SystemVerilog | Xilinx | so-logic (top1) (Austria) | € 1,600.00 | |
12.08. - 16.08.2024 09:00-17:00 | Design Compendium Yocto for AMD Xilinx devices | so-logic | so-logic (top1) (Austria) | € 4,000.00 | |
13.08. - 14.08.2024 09:00-17:00 | Embedded Design with PetaLinux Tools | Xilinx | so-logic (top1) (Austria) | € 1,600.00 | |
02.09. - 03.09.2024 09:00-17:00 | Designing with Versal AI Engine 1 - Architecture and Design Flow | Xilinx | so-logic (top1) (Austria) | € 1,600.00 | |
04.09. - 06.09.2024 09:00-17:00 | Designing with Versal AI Engine 2: Graph Programming with AI Engine Kernels | Xilinx | so-logic (top1) (Austria) | € 2,400.00 | |
09.09. - 13.09.2024 09:00-17:00 | Design Compendium Verfication with VHDL for AMD Xilinx devices | so-logic | so-logic (top1) (Austria) | € 4,000.00 | |
09.09. - 11.09.2024 09:00-17:00 | Designing with Versal AI Engine 3: Kernel Programming and Optimization | Xilinx | so-logic (top1) (Austria) | € 2,400.00 | |
09.09. - 13.09.2024 09:00-17:00 | Design Compendium with Verilog for AMD Xilinx devices | so-logic | so-logic (top1) (Austria) | € 4,000.00 | |
09.09. - 09.09.2024 09:00-17:00 | AMD Versal Compendium 3 : AI Engine | so-logic | so-logic (top1) (Austria) | € 0.00 | |
12.09. - 13.09.2024 09:00-17:00 | Designing with the Versal ACAP: PCI Express Systems | Xilinx | so-logic (top1) (Austria) | € 1,600.00 | |
16.09. - 19.09.2024 09:00-17:00 | Designing with the Versal ACAP: Architecture and Methodology | Xilinx | so-logic (top1) (Austria) | € 3,200.00 | |
16.09. - 20.09.2024 09:00-17:00 | Design Compendium with SystemC for AMD Xilinx devices | so-logic | so-logic (top1) (Austria) | € 4,000.00 | |
20.09. - 20.09.2024 09:00-17:00 | Designing with the Versal ACAP: Network on Chip | Xilinx | so-logic (top1) (Austria) | € 800.00 | |
22.09. - 23.09.2024 09:00-17:00 | Zynq UltraScale+ MPSoC for the System Architect | Xilinx | so-logic (top1) (Austria) | € 1,600.00 | |
23.09. - 27.09.2024 09:00-17:00 | Design Compendium with High Level Synthesis for AMX Xilinx devices | so-logic | so-logic (top1) (Austria) | € 4,000.00 | |
24.09. - 25.09.2024 09:00-17:00 | Zynq UltraScale+ MPSoC for the Software Developer | Xilinx | so-logic (top1) (Austria) | € 1,600.00 | |
26.09. - 26.09.2024 09:00-17:00 | Zynq UltraScale+ MPSoC for the Hardware Designer | Xilinx | so-logic (top1) (Austria) | € 800.00 | |
30.09. - 04.10.2024 09:00-17:00 | Design Compendium with VHDL for AMD Xilinx devices | so-logic | so-logic (top1) (Austria) | € 4,000.00 | |
01.10. - 03.10.2024 09:00-17:00 | Designing with the UltraScale and UltraScale+ Architectures | Xilinx | so-logic (top1) (Austria) | € 2,400.00 | |
04.10. - 08.10.2024 09:00-17:00 | Design Compendium Embedded System for AMD XIlinx devices | so-logic | so-logic (top1) (Austria) | € 4,000.00 | |
06.10. - 07.10.2024 09:00-17:00 | Migrating to the Vitis Embedded Software Development IDE Workshop | Xilinx | so-logic (top1) (Austria) | € 1,600.00 | |
08.10. - 10.10.2024 09:00-17:00 | High-Level Synthesis with Vitis HLS | Xilinx | so-logic (top1) (Austria) | € 2,400.00 | |
13.10. - 14.10.2024 09:00-17:00 | Designing FPGAs Using the Vivado Design Suite 1 | Xilinx | so-logic (top1) (Austria) | € 1,600.00 | |
14.10. - 18.10.2024 09:00-17:00 | Design Compendium Yocto for AMD Xilinx devices | so-logic | so-logic (top1) (Austria) | € 4,000.00 | |
15.10. - 16.10.2024 09:00-17:00 | Designing FPGAs Using the Vivado Design Suite 2 | Xilinx | so-logic (top1) (Austria) | € 1,600.00 | |
20.10. - 21.10.2024 09:00-17:00 | Designing FPGAs Using the Vivado Design Suite 3 | Xilinx | so-logic (top1) (Austria) | € 1,600.00 | |
22.10. - 23.10.2024 09:00-17:00 | Designing FPGAs Using the Vivado Design Suite 4 | Xilinx | so-logic (top1) (Austria) | € 1,600.00 | |
27.10. - 29.10.2024 09:00-17:00 | Designing with VHDL | Xilinx | so-logic (top1) (Austria) | € 2,400.00 | |
30.10. - 31.10.2024 09:00-17:00 | Advanced VHDL | Xilinx | so-logic (top1) (Austria) | € 1,600.00 | |
03.11. - 05.11.2024 09:00-17:00 | Designing with Verilog | Xilinx | so-logic (top1) (Austria) | € 2,400.00 | |
04.11. - 08.11.2024 09:00-17:00 | Design Compendium Verfication with VHDL for AMD Xilinx devices | so-logic | so-logic (top1) (Austria) | € 4,000.00 | |
06.11. - 07.11.2024 09:00-17:00 | Designing with SystemVerilog | Xilinx | so-logic (top1) (Austria) | € 1,600.00 | |
10.11. - 11.11.2024 09:00-17:00 | Verification with SystemVerilog | Xilinx | so-logic (top1) (Austria) | € 1,600.00 | |
11.11. - 15.11.2024 09:00-17:00 | Design Compendium with Verilog for AMD Xilinx devices | so-logic | so-logic (top1) (Austria) | € 4,000.00 | |
12.11. - 13.11.2024 09:00-17:00 | Embedded Design with PetaLinux Tools | Xilinx | so-logic (top1) (Austria) | € 1,600.00 | |
18.11. - 22.11.2024 09:00-17:00 | Design Compendium with SystemC for AMD Xilinx devices | so-logic | so-logic (top1) (Austria) | € 4,000.00 | |
25.11. - 29.11.2024 09:00-17:00 | Design Compendium with High Level Synthesis for AMX Xilinx devices | so-logic | so-logic (top1) (Austria) | € 4,000.00 | |
02.12. - 06.12.2024 09:00-17:00 | Design Compendium with VHDL for AMD Xilinx devices | so-logic | so-logic (top1) (Austria) | € 4,000.00 | |
02.12. - 03.12.2024 09:00-17:00 | Designing with Versal AI Engine 1 - Architecture and Design Flow | Xilinx | so-logic (top1) (Austria) | € 1,600.00 | |
04.12. - 06.12.2024 09:00-17:00 | Designing with Versal AI Engine 2: Graph Programming with AI Engine Kernels | Xilinx | so-logic (top1) (Austria) | € 2,400.00 | |
09.12. - 13.12.2024 09:00-17:00 | Design Compendium Embedded System for AMD XIlinx devices | so-logic | so-logic (top1) (Austria) | € 4,000.00 | |
09.12. - 11.12.2024 09:00-17:00 | Designing with Versal AI Engine 3: Kernel Programming and Optimization | Xilinx | so-logic (top1) (Austria) | € 2,400.00 | |
12.12. - 16.12.2024 09:00-17:00 | Design Compendium Yocto for AMD Xilinx devices | so-logic | so-logic (top1) (Austria) | € 4,000.00 | |
12.12. - 13.12.2024 09:00-17:00 | Designing with the Versal ACAP: PCI Express Systems | Xilinx | so-logic (top1) (Austria) | € 1,600.00 | |
16.12. - 19.12.2024 09:00-17:00 | Designing with the Versal ACAP: Architecture and Methodology | Xilinx | so-logic (top1) (Austria) | € 3,200.00 | |
20.12. - 20.12.2024 09:00-17:00 | Designing with the Versal ACAP: Network on Chip | Xilinx | so-logic (top1) (Austria) | € 0.00 |