Training schedules 2018-12-17 - 2019-12-17

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Event period Training Partner Location Price
14.01. - 15.01.2019 09:00-17:00 Designing FPGAs Using the Vivado Design Suite 1 Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
15.01. - 16.01.2019 09:00-17:00 Designing with the UltraScale and UltraScale+ Architectures Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
15.01. - 16.01.2019 09:00-17:00 Designing with 7 Series Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
16.01. - 17.01.2019 09:00-17:00 Designing FPGAs Using the Vivado Design Suite 2 Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
21.01. - 22.01.2019 09:00-17:00 Designing FPGAs Using the Vivado Design Suite 3 Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
21.01. - 22.01.2019 09:00-17:00 Partial Reconfiguration Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
23.01. - 24.01.2019 09:00-17:00 Designing FPGAs Using the Vivado Design Suite 4 Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
23.01. - 25.01.2019 09:00-17:00 Vivado Design Suite Advanced XDC and Timing Analysis for ISE Users Xilinx so-logic (top1) (Austria) € 2,250.00 Add to cart
23.01. - 24.01.2019 09:00-17:00 C-based Design: High-Level Synthesis with Vivado HLS Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
28.01. - 29.01.2019 09:00-17:00 Embedded Systems Software Design Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
29.01. - 30.01.2019 09:00-17:00 Embedded Systems Design Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
30.01. - 30.01.2019 09:00-17:00 Advanced Features and Techniques of Embedded Systems Software Design Xilinx so-logic (top1) (Austria) € 750.00 Add to cart
31.01. - 01.02.2019 09:00-17:00 Advanced Features and Techniques of Embedded Systems Design Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
04.02. - 06.02.2019 09:00-17:00 Embedded Open-Source Linux Development so-logic so-logic (top1) (Austria) € 2,250.00 Add to cart
04.02. - 05.02.2019 09:00-17:00 Zynq UltraScale+ MPSoC for the Software Developer Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
06.02. - 07.02.2019 09:00-17:00 Zynq UltraScale+ MPSoC for the System Architect Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
07.02. - 08.02.2019 09:00-17:00 Developing and Optimizing Applications Using the OpenCL Framework for FPGAs Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
08.02. - 08.02.2019 09:00-17:00 Zynq UltraScale+ MPSoC for the Hardware Designer Xilinx so-logic (top1) (Austria) € 750.00 Add to cart
11.02. - 13.02.2019 09:00-17:00 Designing with Multi-Gigabit Serial I/O Xilinx so-logic (top1) (Austria) € 2,250.00 Add to cart
12.02. - 13.02.2019 09:00-17:00 Designing with UltraScale FPGA Transceivers Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
14.02. - 15.02.2019 09:00-17:00 Designing with Ethernet MAC Controllers Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
14.02. - 15.02.2019 09:00-17:00 Designing a LogiCORE PCI Express System Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
14.02. - 15.02.2019 09:00-17:00 Connectivity Memory Interfaces Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
18.02. - 20.02.2019 09:00-17:00 Designing with VHDL Xilinx so-logic (top1) (Austria) € 2,250.00 Add to cart
18.02. - 20.02.2019 09:00-17:00 Designing with Verilog Xilinx so-logic (top1) (Austria) € 2,250.00 Add to cart
19.02. - 20.02.2019 09:00-17:00 Designing with System Verilog Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
21.02. - 22.02.2019 09:00-17:00 Advanced VHDL Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
21.02. - 22.02.2019 09:00-17:00 Verification with System Verilog Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
25.02. - 26.02.2019 09:00-17:00 Essential DSP Implementation Techniques for Xilinx FPGAs Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
27.02. - 28.02.2019 09:00-17:00 DSP Design Using System Generator Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
27.02. - 28.02.2019 09:00-17:00 C-based Design: High-Level Synthesis with Vivado HLS Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
01.03. - 01.03.2019 09:00-17:00 C-based HLS Coding for Software Designers Xilinx so-logic (top1) (Austria) € 750.00 Add to cart
01.03. - 01.03.2019 09:00-17:00 C-based HLS Coding for Hardware Designers Xilinx so-logic (top1) (Austria) € 750.00 Add to cart
04.03. - 05.03.2019 09:00-17:00 Designing FPGAs Using the Vivado Design Suite 1 Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
05.03. - 06.03.2019 09:00-17:00 Designing with 7 Series Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
05.03. - 06.03.2019 09:00-17:00 Designing with the UltraScale and UltraScale+ Architectures Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
06.03. - 07.03.2019 09:00-17:00 Designing FPGAs Using the Vivado Design Suite 2 Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
11.03. - 12.03.2019 09:00-17:00 Designing FPGAs Using the Vivado Design Suite 3 Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
11.03. - 12.03.2019 09:00-17:00 Partial Reconfiguration Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
13.03. - 15.03.2019 09:00-17:00 Vivado Design Suite Advanced XDC and Timing Analysis for ISE Users Xilinx so-logic (top1) (Austria) € 2,250.00 Add to cart
13.03. - 14.03.2019 09:00-17:00 Designing FPGAs Using the Vivado Design Suite 4 Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
18.03. - 19.03.2019 09:00-17:00 Embedded Systems Software Design Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
19.03. - 20.03.2019 09:00-17:00 Embedded Systems Design Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
20.03. - 20.03.2019 09:00-17:00 Advanced Features and Techniques of Embedded Systems Software Design Xilinx so-logic (top1) (Austria) € 750.00 Add to cart
21.03. - 22.03.2019 09:00-17:00 Advanced Features and Techniques of Embedded Systems Design Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
25.03. - 27.03.2019 09:00-17:00 Embedded Open-Source Linux Development so-logic so-logic (top1) (Austria) € 2,250.00 Add to cart
25.03. - 26.03.2019 09:00-17:00 Zynq UltraScale+ MPSoC for the Software Developer Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
27.03. - 28.03.2019 09:00-17:00 Zynq UltraScale+ MPSoC for the System Architect Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
28.03. - 29.03.2019 09:00-17:00 Developing and Optimizing Applications Using the OpenCL Framework for FPGAs Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
29.03. - 29.03.2019 09:00-17:00 Zynq UltraScale+ MPSoC for the Hardware Designer Xilinx so-logic (top1) (Austria) € 750.00 Add to cart
01.04. - 03.04.2019 09:00-17:00 Designing with Multi-Gigabit Serial I/O Xilinx so-logic (top1) (Austria) € 2,250.00 Add to cart
02.04. - 03.04.2019 09:00-17:00 Designing with UltraScale FPGA Transceivers Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
04.04. - 05.04.2019 09:00-17:00 Designing a LogiCORE PCI Express System Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
04.04. - 05.04.2019 09:00-17:00 Designing with Ethernet MAC Controllers Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
04.04. - 05.04.2019 09:00-17:00 Connectivity Memory Interfaces Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
08.04. - 09.04.2019 09:00-17:00 Essential DSP Implementation Techniques for Xilinx FPGAs Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
10.04. - 11.04.2019 09:00-17:00 C-based Design: High-Level Synthesis with Vivado HLS Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
10.04. - 11.04.2019 09:00-17:00 DSP Design Using System Generator Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
12.04. - 12.04.2019 09:00-17:00 C-based HLS Coding for Software Designers Xilinx so-logic (top1) (Austria) € 750.00 Add to cart
12.04. - 12.04.2019 09:00-17:00 C-based HLS Coding for Hardware Designers Xilinx so-logic (top1) (Austria) € 750.00 Add to cart
15.04. - 17.04.2019 09:00-17:00 Designing with Verilog Xilinx so-logic (top1) (Austria) € 2,250.00 Add to cart
15.04. - 17.04.2019 09:00-17:00 Designing with VHDL Xilinx so-logic (top1) (Austria) € 2,250.00 Add to cart
16.04. - 17.04.2019 09:00-17:00 Designing with System Verilog Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
18.04. - 19.04.2019 09:00-17:00 Advanced VHDL Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
18.04. - 19.04.2019 09:00-17:00 Verification with System Verilog Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
23.04. - 24.04.2019 09:00-17:00 Designing with the UltraScale and UltraScale+ Architectures Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
23.04. - 24.04.2019 09:00-17:00 Designing FPGAs Using the Vivado Design Suite 1 Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
23.04. - 24.04.2019 09:00-17:00 Designing with 7 Series Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
25.04. - 26.04.2019 09:00-17:00 Designing FPGAs Using the Vivado Design Suite 2 Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
29.04. - 30.04.2019 09:00-17:00 Embedded Systems Software Design Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
29.04. - 30.04.2019 09:00-17:00 Partial Reconfiguration Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
29.04. - 30.04.2019 09:00-17:00 Designing FPGAs Using the Vivado Design Suite 3 Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
29.04. - 30.04.2019 09:00-17:00 Embedded Systems Design Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
01.05. - 02.05.2019 09:00-17:00 Designing FPGAs Using the Vivado Design Suite 4 Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
01.05. - 03.05.2019 09:00-17:00 Vivado Design Suite Advanced XDC and Timing Analysis for ISE Users Xilinx so-logic (top1) (Austria) € 2,250.00 Add to cart
02.05. - 02.05.2019 09:00-17:00 Advanced Features and Techniques of Embedded Systems Software Design Xilinx so-logic (top1) (Austria) € 750.00 Add to cart
02.05. - 03.05.2019 09:00-17:00 Advanced Features and Techniques of Embedded Systems Design Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
06.05. - 08.05.2019 09:00-17:00 Embedded Open-Source Linux Development so-logic so-logic (top1) (Austria) € 2,250.00 Add to cart
06.05. - 07.05.2019 09:00-17:00 Zynq UltraScale+ MPSoC for the Software Developer Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
08.05. - 09.05.2019 09:00-17:00 Zynq UltraScale+ MPSoC for the System Architect Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
09.05. - 10.05.2019 09:00-17:00 Developing and Optimizing Applications Using the OpenCL Framework for FPGAs Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
13.05. - 15.05.2019 09:00-17:00 Designing with Multi-Gigabit Serial I/O Xilinx so-logic (top1) (Austria) € 2,250.00 Add to cart
14.05. - 15.05.2019 09:00-17:00 Designing with UltraScale FPGA Transceivers Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
16.05. - 17.05.2019 09:00-17:00 Designing with Ethernet MAC Controllers Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
16.05. - 17.05.2019 09:00-17:00 Connectivity Memory Interfaces Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
16.05. - 17.05.2019 09:00-17:00 Designing a LogiCORE PCI Express System Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
20.05. - 22.05.2019 09:00-17:00 Designing with VHDL Xilinx so-logic (top1) (Austria) € 2,250.00 Add to cart
20.05. - 22.05.2019 09:00-17:00 Designing with Verilog Xilinx so-logic (top1) (Austria) € 2,250.00 Add to cart
21.05. - 22.05.2019 09:00-17:00 Designing with System Verilog Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
23.05. - 24.05.2019 09:00-17:00 Verification with System Verilog Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
23.05. - 24.05.2019 09:00-17:00 Advanced VHDL Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
27.05. - 28.05.2019 09:00-17:00 Essential DSP Implementation Techniques for Xilinx FPGAs Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
28.05. - 29.05.2019 09:00-17:00 C-based Design: High-Level Synthesis with Vivado HLS Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
28.05. - 29.05.2019 09:00-17:00 DSP Design Using System Generator Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
31.05. - 31.05.2019 09:00-17:00 C-based HLS Coding for Hardware Designers Xilinx so-logic (top1) (Austria) € 750.00 Add to cart
31.05. - 31.05.2019 09:00-17:00 C-based HLS Coding for Software Designers Xilinx so-logic (top1) (Austria) € 750.00 Add to cart
03.06. - 04.06.2019 09:00-17:00 Designing FPGAs Using the Vivado Design Suite 1 Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
04.06. - 05.06.2019 09:00-17:00 Designing with the UltraScale and UltraScale+ Architectures Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
04.06. - 05.06.2019 09:00-17:00 Designing with 7 Series Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
05.06. - 06.06.2019 09:00-17:00 Designing FPGAs Using the Vivado Design Suite 2 Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
11.06. - 12.06.2019 09:00-17:00 Designing FPGAs Using the Vivado Design Suite 3 Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
11.06. - 12.06.2019 09:00-17:00 Partial Reconfiguration Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
12.06. - 14.06.2019 09:00-17:00 Vivado Design Suite Advanced XDC and Timing Analysis for ISE Users Xilinx so-logic (top1) (Austria) € 2,250.00 Add to cart
13.06. - 14.06.2019 09:00-17:00 Designing FPGAs Using the Vivado Design Suite 4 Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
17.06. - 18.06.2019 09:00-17:00 Embedded Systems Software Design Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
18.06. - 19.06.2019 09:00-17:00 Embedded Systems Design Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
19.06. - 19.06.2019 09:00-17:00 Advanced Features and Techniques of Embedded Systems Software Design Xilinx so-logic (top1) (Austria) € 750.00 Add to cart
20.06. - 21.06.2019 09:00-17:00 Advanced Features and Techniques of Embedded Systems Design Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
24.06. - 25.06.2019 09:00-17:00 Zynq UltraScale+ MPSoC for the Software Developer Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
24.06. - 26.06.2019 09:00-17:00 Embedded Open-Source Linux Development so-logic so-logic (top1) (Austria) € 2,250.00 Add to cart
26.06. - 27.06.2019 09:00-17:00 Zynq UltraScale+ MPSoC for the System Architect Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
27.06. - 28.06.2019 09:00-17:00 Developing and Optimizing Applications Using the OpenCL Framework for FPGAs Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
28.06. - 28.06.2019 09:00-17:00 Zynq UltraScale+ MPSoC for the Hardware Designer Xilinx so-logic (top1) (Austria) € 750.00 Add to cart
08.07. - 10.07.2019 09:00-17:00 Designing with Multi-Gigabit Serial I/O Xilinx so-logic (top1) (Austria) € 2,250.00 Add to cart
09.07. - 10.07.2019 09:00-17:00 Designing with UltraScale FPGA Transceivers Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
11.07. - 12.07.2019 09:00-17:00 Designing a LogiCORE PCI Express System Xilinx so-logic (Brazil) € 1,500.00 Add to cart
11.07. - 12.07.2019 09:00-17:00 Connectivity Memory Interfaces Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
11.07. - 12.07.2019 09:00-17:00 Designing with Ethernet MAC Controllers Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
15.07. - 17.07.2019 09:00-17:00 Designing with Verilog Xilinx so-logic (top1) (Austria) € 2,250.00 Add to cart
15.07. - 17.07.2019 09:00-17:00 Designing with VHDL Xilinx so-logic (top1) (Austria) € 2,250.00 Add to cart
16.07. - 17.07.2019 09:00-17:00 Designing with System Verilog Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
18.07. - 19.07.2019 09:00-17:00 Advanced VHDL Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
18.07. - 19.07.2019 09:00-17:00 Verification with System Verilog Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
22.07. - 23.07.2019 09:00-17:00 Essential DSP Implementation Techniques for Xilinx FPGAs Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
24.07. - 25.07.2019 09:00-17:00 C-based Design: High-Level Synthesis with Vivado HLS Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
24.07. - 25.07.2019 09:00-17:00 DSP Design Using System Generator Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
26.07. - 26.07.2019 09:00-17:00 C-based HLS Coding for Hardware Designers Xilinx so-logic (top1) (Austria) € 750.00 Add to cart
26.07. - 26.07.2019 09:00-17:00 C-based HLS Coding for Software Designers Xilinx so-logic (top1) (Austria) € 750.00 Add to cart
29.07. - 30.07.2019 09:00-17:00 Designing FPGAs Using the Vivado Design Suite 3 Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
29.07. - 30.07.2019 09:00-17:00 Designing FPGAs Using the Vivado Design Suite 1 Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
29.07. - 30.07.2019 09:00-17:00 Partial Reconfiguration Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
30.07. - 31.07.2019 09:00-17:00 Designing with 7 Series Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
30.07. - 31.07.2019 09:00-17:00 Designing with the UltraScale and UltraScale+ Architectures Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
31.07. - 02.08.2019 09:00-17:00 Vivado Design Suite Advanced XDC and Timing Analysis for ISE Users Xilinx so-logic (top1) (Austria) € 2,250.00 Add to cart
31.07. - 01.08.2019 09:00-17:00 Designing FPGAs Using the Vivado Design Suite 4 Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
31.07. - 01.08.2019 09:00-17:00 Designing FPGAs Using the Vivado Design Suite 2 Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
05.08. - 06.08.2019 09:00-17:00 Embedded Systems Software Design Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
06.08. - 07.08.2019 09:00-17:00 Embedded Systems Design Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
07.08. - 07.08.2019 09:00-17:00 Advanced Features and Techniques of Embedded Systems Software Design Xilinx so-logic (top1) (Austria) € 750.00 Add to cart
12.08. - 14.08.2019 09:00-17:00 Embedded Open-Source Linux Development so-logic so-logic (top1) (Austria) € 2,250.00 Add to cart
12.08. - 13.08.2019 09:00-17:00 Zynq UltraScale+ MPSoC for the Software Developer Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
14.08. - 15.08.2019 09:00-17:00 Zynq UltraScale+ MPSoC for the System Architect Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
15.08. - 16.08.2019 09:00-17:00 Developing and Optimizing Applications Using the OpenCL Framework for FPGAs Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
16.08. - 16.08.2019 09:00-17:00 Zynq UltraScale+ MPSoC for the Hardware Designer Xilinx so-logic (top1) (Austria) € 750.00 Add to cart
19.08. - 21.08.2019 09:00-17:00 Designing with Multi-Gigabit Serial I/O Xilinx so-logic (top1) (Austria) € 2,250.00 Add to cart
20.08. - 21.08.2019 09:00-17:00 Designing with UltraScale FPGA Transceivers Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
22.08. - 23.08.2019 09:00-17:00 Connectivity Memory Interfaces Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
22.08. - 23.08.2019 09:00-17:00 Designing a LogiCORE PCI Express System Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
22.08. - 23.08.2019 09:00-17:00 Designing with Ethernet MAC Controllers Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
26.08. - 28.08.2019 09:00-17:00 Designing with Verilog Xilinx so-logic (top1) (Austria) € 2,250.00 Add to cart
26.08. - 28.08.2019 09:00-17:00 Designing with VHDL Xilinx so-logic (top1) (Austria) € 2,250.00 Add to cart
27.08. - 28.08.2019 09:00-17:00 Designing with System Verilog Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
29.08. - 30.08.2019 09:00-17:00 Verification with System Verilog Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
29.08. - 30.08.2019 09:00-17:00 Advanced VHDL Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
02.09. - 03.09.2019 09:00-17:00 Essential DSP Implementation Techniques for Xilinx FPGAs Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
04.09. - 05.09.2019 09:00-17:00 DSP Design Using System Generator Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
04.09. - 05.09.2019 09:00-17:00 C-based Design: High-Level Synthesis with Vivado HLS Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
06.09. - 06.09.2019 09:00-17:00 C-based HLS Coding for Software Designers Xilinx so-logic (top1) (Austria) € 750.00 Add to cart
06.09. - 06.09.2019 09:00-17:00 C-based HLS Coding for Hardware Designers Xilinx so-logic (top1) (Austria) € 750.00 Add to cart
09.09. - 10.09.2019 09:00-17:00 Designing FPGAs Using the Vivado Design Suite 1 Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
10.09. - 11.09.2019 09:00-17:00 Designing with the UltraScale and UltraScale+ Architectures Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
10.09. - 11.09.2019 09:00-17:00 Designing with 7 Series Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
11.09. - 12.09.2019 09:00-17:00 Designing FPGAs Using the Vivado Design Suite 2 Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
16.09. - 17.09.2019 09:00-17:00 Partial Reconfiguration Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
16.09. - 17.09.2019 09:00-17:00 Designing FPGAs Using the Vivado Design Suite 3 Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
18.09. - 20.09.2019 09:00-17:00 Vivado Design Suite Advanced XDC and Timing Analysis for ISE Users Xilinx so-logic (top1) (Austria) € 2,250.00 Add to cart
18.09. - 19.09.2019 09:00-17:00 Designing FPGAs Using the Vivado Design Suite 4 Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
23.09. - 24.09.2019 09:00-17:00 Embedded Systems Software Design Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
24.09. - 25.09.2019 09:00-17:00 Embedded Systems Design Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
25.09. - 25.09.2019 09:00-17:00 Advanced Features and Techniques of Embedded Systems Software Design Xilinx so-logic (top1) (Austria) € 750.00 Add to cart
26.09. - 27.09.2019 09:00-17:00 Advanced Features and Techniques of Embedded Systems Design Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
30.09. - 02.10.2019 09:00-17:00 Embedded Open-Source Linux Development so-logic so-logic (top1) (Austria) € 2,250.00 Add to cart
30.09. - 01.10.2019 09:00-17:00 Zynq UltraScale+ MPSoC for the Software Developer Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
02.10. - 03.10.2019 09:00-17:00 Zynq UltraScale+ MPSoC for the System Architect Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
03.10. - 04.10.2019 09:00-17:00 Developing and Optimizing Applications Using the OpenCL Framework for FPGAs Xilinx so-logic (top1) (Austria) € 750.00 Add to cart
04.10. - 04.10.2019 09:00-17:00 Zynq UltraScale+ MPSoC for the Hardware Designer Xilinx so-logic (top1) (Austria) € 750.00 Add to cart
07.10. - 09.10.2019 09:00-17:00 Designing with Multi-Gigabit Serial I/O Xilinx so-logic (top1) (Austria) € 2,250.00 Add to cart
08.10. - 09.10.2019 09:00-17:00 Designing with UltraScale FPGA Transceivers Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
10.10. - 11.10.2019 09:00-17:00 Designing a LogiCORE PCI Express System Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
10.10. - 11.10.2019 09:00-17:00 Designing with Ethernet MAC Controllers Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
10.10. - 11.10.2019 09:00-17:00 Connectivity Memory Interfaces Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
14.10. - 16.10.2019 09:00-17:00 Designing with VHDL Xilinx so-logic (top1) (Austria) € 2,250.00 Add to cart
14.10. - 16.10.2019 09:00-17:00 Designing with Verilog Xilinx so-logic (top1) (Austria) € 2,250.00 Add to cart
15.10. - 16.10.2019 09:00-17:00 Designing with System Verilog Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
17.10. - 18.10.2019 09:00-17:00 Verification with System Verilog Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
17.10. - 18.10.2019 09:00-17:00 Advanced VHDL Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
21.10. - 22.10.2019 09:00-17:00 Essential DSP Implementation Techniques for Xilinx FPGAs Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
23.10. - 24.10.2019 09:00-17:00 DSP Design Using System Generator Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
23.10. - 24.10.2019 09:00-17:00 C-based Design: High-Level Synthesis with Vivado HLS Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
25.10. - 25.10.2019 09:00-17:00 C-based HLS Coding for Hardware Designers Xilinx so-logic (top1) (Austria) € 750.00 Add to cart
25.10. - 25.10.2019 09:00-17:00 C-based HLS Coding for Software Designers Xilinx so-logic (top1) (Austria) € 750.00 Add to cart
28.10. - 29.10.2019 09:00-17:00 Designing FPGAs Using the Vivado Design Suite 1 Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
28.10. - 29.10.2019 09:00-17:00 Designing with the UltraScale and UltraScale+ Architectures Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
28.10. - 29.10.2019 09:00-17:00 Designing with 7 Series Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
30.10. - 31.10.2019 09:00-17:00 Designing FPGAs Using the Vivado Design Suite 2 Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
04.11. - 05.11.2019 09:00-17:00 Partial Reconfiguration Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
04.11. - 05.11.2019 09:00-17:00 Designing FPGAs Using the Vivado Design Suite 3 Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
06.11. - 08.11.2019 09:00-17:00 Vivado Design Suite Advanced XDC and Timing Analysis for ISE Users Xilinx so-logic (top1) (Austria) € 2,250.00 Add to cart
06.11. - 07.11.2019 09:00-17:00 Designing FPGAs Using the Vivado Design Suite 4 Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
11.11. - 12.11.2019 09:00-17:00 Embedded Systems Software Design Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
12.11. - 13.11.2019 09:00-17:00 Embedded Systems Design Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
13.11. - 13.11.2019 09:00-17:00 Advanced Features and Techniques of Embedded Systems Software Design Xilinx so-logic (top1) (Austria) € 750.00 Add to cart
14.11. - 15.11.2019 09:00-17:00 Advanced Features and Techniques of Embedded Systems Design Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
18.11. - 19.11.2019 09:00-17:00 Zynq UltraScale+ MPSoC for the Software Developer Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
18.11. - 20.11.2019 09:00-17:00 Embedded Open-Source Linux Development so-logic so-logic (top1) (Austria) € 2,250.00 Add to cart
20.11. - 21.11.2019 09:00-17:00 Zynq UltraScale+ MPSoC for the System Architect Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
21.11. - 22.11.2019 09:00-17:00 Developing and Optimizing Applications Using the OpenCL Framework for FPGAs Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
22.11. - 22.11.2019 09:00-17:00 Zynq UltraScale+ MPSoC for the Hardware Designer Xilinx so-logic (top1) (Austria) € 750.00 Add to cart
25.11. - 27.11.2019 09:00-17:00 Designing with Multi-Gigabit Serial I/O Xilinx so-logic (top1) (Austria) € 2,250.00 Add to cart
26.11. - 27.11.2019 09:00-17:00 Designing with UltraScale FPGA Transceivers Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
28.11. - 29.11.2019 09:00-17:00 Designing with Ethernet MAC Controllers Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
28.11. - 29.11.2019 09:00-17:00 Connectivity Memory Interfaces Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
28.11. - 29.11.2019 09:00-17:00 Designing a LogiCORE PCI Express System Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
02.12. - 04.12.2019 09:00-17:00 Designing with VHDL Xilinx so-logic (top1) (Austria) € 2,250.00 Add to cart
02.12. - 04.12.2019 09:00-17:00 Designing with Verilog Xilinx so-logic (top1) (Austria) € 2,250.00 Add to cart
03.12. - 04.12.2019 09:00-17:00 Designing with System Verilog Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
05.12. - 06.12.2019 09:00-17:00 Advanced VHDL Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
05.12. - 06.12.2019 09:00-17:00 Verification with System Verilog Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
09.12. - 10.12.2019 09:00-17:00 Essential DSP Implementation Techniques for Xilinx FPGAs Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
11.12. - 12.12.2019 09:00-17:00 C-based Design: High-Level Synthesis with Vivado HLS Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
11.12. - 12.12.2019 09:00-17:00 DSP Design Using System Generator Xilinx so-logic (top1) (Austria) € 1,500.00 Add to cart
13.12. - 13.12.2019 09:00-17:00 C-based HLS Coding for Software Designers Xilinx so-logic (top1) (Austria) € 750.00 Add to cart
13.12. - 13.12.2019 09:00-17:00 C-based HLS Coding for Hardware Designers Xilinx so-logic (top1) (Austria) € 750.00 Add to cart