Training schedules 2025-01-24 - 2026-01-24
Event period | Training | Partner | Location | Price | |
---|---|---|---|---|---|
23.12. - 24.12.2025 09:00-17:00 | Designing with the Versal Adaptive SoC: Memory Interfaces | Xilinx | Virtual Learning Environment (Online) | € 1,700.00 | |
22.12. - 22.12.2025 09:00-17:00 | Designing with the Versal Adaptive SoC: Network on Chip | Xilinx | Virtual Learning Environment (Online) | € 850.00 | |
17.12. - 18.12.2025 09:00-17:00 | Designing with the Versal Adaptive SoC: Hardware Debug | Xilinx | Virtual Learning Environment (Online) | € 1,700.00 | |
16.12. - 17.12.2025 09:00-17:00 | Designing with the Versal Adaptive SoC: Architecture | Xilinx | Virtual Learning Environment (Online) | € 1,700.00 | |
15.12. - 19.12.2025 09:00-17:00 | Design Compendium with High Level Synthesis for AMD Xilinx devices | so-logic | Virtual Learning Environment (Online) | € 4,250.00 | |
11.12. - 12.12.2025 09:00-17:00 | Developing AI Inference Solutions with the Vitis AI Platform | Xilinx | Virtual Learning Environment (Online) | € 1,700.00 | |
09.12. - 10.12.2025 09:00-17:00 | Designing with Versal AI Engine: Kernel Programming and Optimization - 3 | Xilinx | Virtual Learning Environment (Online) | € 1,700.00 | |
08.12. - 12.12.2025 09:00-17:00 | Design Compendium Verification with VHDL for AMD Xilinx devices | so-logic | Virtual Learning Environment (Online) | € 1,700.00 | |
04.12. - 05.12.2025 09:00-17:00 | Designing with Versal AI Engine: Graph Programming with AI Engine Kernels - 2 | Xilinx | Virtual Learning Environment (Online) | € 1,700.00 | |
02.12. - 03.12.2025 09:00-17:00 | Designing with Versal AI Engine: Architecture and Design Flow - 1 | Xilinx | Virtual Learning Environment (Online) | € 1,700.00 | |
01.12. - 05.12.2025 09:00-17:00 | Design Compendium Yocto for AMD Xilinx devices | so-logic | Virtual Learning Environment (Online) | € 4,250.00 | |
27.11. - 28.11.2025 09:00-17:00 | Designing with Ethernet MAC Controllers | Xilinx | Virtual Learning Environment (Online) | € 1,700.00 | |
26.11. - 26.11.2025 09:00-17:00 | Designing with the Versal Adaptive SoC: Serial Transceivers | Xilinx | Virtual Learning Environment (Online) | € 850.00 | |
24.11. - 25.11.2025 09:00-17:00 | Designing with Xilinx Serial Transceivers | Xilinx | Virtual Learning Environment (Online) | € 1,700.00 | |
24.11. - 28.11.2025 09:00-17:00 | Design Compendium with Verilog for AMD Xilinx devices | so-logic | Virtual Learning Environment (Online) | € 1,700.00 | |
20.11. - 21.11.2025 09:00-17:00 | DFX - Designing with Dynamic Function eXchange Using the Vivado Design Suite | Xilinx | Virtual Learning Environment (Online) | € 1,700.00 | |
17.11. - 19.11.2025 09:00-17:00 | Design Compendium with VHDL for AMD Xilinx devices | so-logic | Virtual Learning Environment (Online) | € 4,250.00 | |
13.11. - 14.11.2025 09:00-17:00 | Embedded Design with PetaLinux Tools | Xilinx | Virtual Learning Environment (Online) | € 1,700.00 | |
11.11. - 12.11.2025 09:00-17:00 | Designing with the Zynq UltraScale+ RFSoC | Xilinx | Virtual Learning Environment (Online) | € 1,700.00 | |
10.11. - 14.11.2025 09:00-17:00 | Design Compendium Embedded System for AMD XIlinx devices | so-logic | Virtual Learning Environment (Online) | € 4,250.00 | |
06.11. - 07.11.2025 09:00-17:00 | Operating Systems and Hypervisors in Adaptive SoCs | Xilinx | Virtual Learning Environment (Online) | € 1,700.00 | |
04.11. - 05.11.2025 09:00-17:00 | Embedded Heterogeneous Design | Xilinx | Virtual Learning Environment (Online) | € 1,700.00 | |
03.11. - 07.11.2025 09:00-17:00 | Design Compendium with High Level Synthesis for AMD Xilinx devices | so-logic | Virtual Learning Environment (Online) | € 4,250.00 | |
30.10. - 31.10.2025 09:00-17:00 | Vitis Model Composer: A MATLAB and Simulink-based Product | Xilinx | Virtual Learning Environment (Online) | € 1,700.00 | |
30.10. - 31.10.2025 09:00-17:00 | Verification with SystemVerilog | Xilinx | Virtual Learning Environment (Online) | € 1,700.00 | |
28.10. - 29.10.2025 09:00-17:00 | Designing with SystemVerilog | Xilinx | Virtual Learning Environment (Online) | € 1,700.00 | |
27.10. - 31.10.2025 09:00-17:00 | Design Compendium Verification with VHDL for AMD Xilinx devices | so-logic | Virtual Learning Environment (Online) | € 4,250.00 | |
27.10. - 29.10.2025 09:00-17:00 | Designing with Verilog | Xilinx | Virtual Learning Environment (Online) | € 1,700.00 | |
21.10. - 22.10.2025 09:00-17:00 | High-Level Synthesis with the Vitis Unified IDE (HLS) | Xilinx | Virtual Learning Environment (Online) | € 1,700.00 | |
20.10. - 24.10.2025 09:00-17:00 | Design Compendium Yocto for AMD Xilinx devices | so-logic | Virtual Learning Environment (Online) | € 4,250.00 | |
16.10. - 17.10.2025 09:00-17:00 | Designing FPGAs Using the Vivado Design Suite 4 | Xilinx | Virtual Learning Environment (Online) | € 1,700.00 | |
14.10. - 15.10.2025 09:00-17:00 | Designing FPGAs Using the Vivado Design Suite 3 | Xilinx | Virtual Learning Environment (Online) | € 1,700.00 | |
13.10. - 17.10.2025 09:00-17:00 | Design Compendium with Verilog for AMD Xilinx devices | so-logic | Virtual Learning Environment (Online) | € 4,259.00 | |
09.10. - 10.10.2025 09:00-17:00 | Designing FPGAs Using the Vivado Design Suite 2 | Xilinx | Virtual Learning Environment (Online) | € 1,700.00 | |
07.10. - 08.10.2025 09:00-17:00 | Designing FPGAs Using the Vivado Design Suite 1 | Xilinx | Virtual Learning Environment (Online) | € 1,700.00 | |
06.10. - 08.10.2025 09:00-17:00 | Design Compendium with VHDL for AMD Xilinx devices | so-logic | Virtual Learning Environment (Online) | € 4,250.00 | |
02.10. - 03.10.2025 09:00-17:00 | Designing an Integrated PCI Express System | Xilinx | Virtual Learning Environment (Online) | € 1,700.00 | |
30.09. - 01.10.2025 09:00-17:00 | Designing with the Versal Adaptive SoC: PCI Express Systems | Xilinx | Virtual Learning Environment (Online) | € 1,700.00 | |
29.09. - 29.09.2025 09:00-17:00 | PCIe Protocol | Xilinx | Virtual Learning Environment (Online) | € 850.00 | |
25.09. - 26.09.2025 09:00-17:00 | Designing with the Versal Adaptive SoC: Power and Board Design | Xilinx | Virtual Learning Environment (Online) | € 1,700.00 | |
23.09. - 24.09.2025 09:00-17:00 | Designing with the Versal Adaptive SoC: Memory Interfaces | Xilinx | Virtual Learning Environment (Online) | € 1,700.00 | |
22.09. - 26.09.2025 09:00-17:00 | Design Compendium Embedded System for AMD XIlinx devices | so-logic | Virtual Learning Environment (Online) | € 4,250.00 | |
22.09. - 22.09.2025 09:00-17:00 | Designing with the Versal Adaptive SoC: Network on Chip | Xilinx | Virtual Learning Environment (Online) | € 850.00 | |
20.09. - 21.09.2025 09:00-17:00 | Designing with the Versal Adaptive SoC: Architecture | Xilinx | Virtual Learning Environment (Online) | € 1,700.00 | |
17.09. - 18.09.2025 09:00-17:00 | Designing with the Versal Adaptive SoC: Hardware Debug | Xilinx | Virtual Learning Environment (Online) | € 1,700.00 | |
15.09. - 19.09.2025 09:00-17:00 | Design Compendium with High Level Synthesis for AMD Xilinx devices | so-logic | Virtual Learning Environment (Online) | € 4,250.00 | |
11.09. - 12.09.2025 09:00-17:00 | Developing AI Inference Solutions with the Vitis AI Platform | Xilinx | Virtual Learning Environment (Online) | € 1,700.00 | |
09.09. - 10.09.2025 09:00-17:00 | Designing with Versal AI Engine: Kernel Programming and Optimization - 3 | Xilinx | Virtual Learning Environment (Online) | € 1,700.00 | |
09.09. - 13.09.2025 09:00-17:00 | Design Compendium with SystemC for AMD Xilinx devices | so-logic | Virtual Learning Environment (Online) | € 4,250.00 | |
08.09. - 12.09.2025 09:00-17:00 | Design Compendium Verification with VHDL for AMD Xilinx devices | so-logic | Virtual Learning Environment (Online) | € 1,700.00 | |
04.09. - 05.09.2025 09:00-17:00 | Designing with Versal AI Engine: Graph Programming with AI Engine Kernels - 2 | Xilinx | Virtual Learning Environment (Online) | € 1,700.00 | |
02.09. - 03.09.2025 09:00-17:00 | Designing with Versal AI Engine: Architecture and Design Flow - 1 | Xilinx | Virtual Learning Environment (Online) | € 1,700.00 | |
01.09. - 05.09.2025 09:00-17:00 | Design Compendium Yocto for AMD Xilinx devices | so-logic | Virtual Learning Environment (Online) | € 4,250.00 | |
28.08. - 29.08.2025 09:00-17:00 | Designing with Ethernet MAC Controllers | Xilinx | Virtual Learning Environment (Online) | € 1,700.00 | |
27.08. - 27.08.2025 09:00-17:00 | Designing with the Versal Adaptive SoC: Serial Transceivers | Xilinx | Virtual Learning Environment (Online) | € 850.00 | |
25.08. - 29.08.2025 09:00-17:00 | Design Compendium with Verilog for AMD Xilinx devices | so-logic | Virtual Learning Environment (Online) | € 1,700.00 | |
25.08. - 26.08.2025 09:00-17:00 | Designing with Xilinx Serial Transceivers | Xilinx | Virtual Learning Environment (Online) | € 1,700.00 | |
22.08. - 23.08.2025 09:00-17:00 | High-Level Synthesis with the Vitis Unified IDE (HLS) | Xilinx | Virtual Learning Environment (Online) | € 1,700.00 | |
21.08. - 22.08.2025 09:00-17:00 | DFX - Designing with Dynamic Function eXchange Using the Vivado Design Suite | Xilinx | Virtual Learning Environment (Online) | € 1,700.00 | |
18.08. - 20.08.2025 09:00-17:00 | Design Compendium with VHDL for AMD Xilinx devices | so-logic | Virtual Learning Environment (Online) | € 4,250.00 | |
14.08. - 15.08.2025 09:00-17:00 | Embedded Design with PetaLinux Tools | Xilinx | Virtual Learning Environment (Online) | € 1,700.00 | |
12.08. - 13.08.2025 09:00-17:00 | Designing with the Zynq UltraScale+ RFSoC | Xilinx | Virtual Learning Environment (Online) | € 1,700.00 | |
11.08. - 15.08.2025 09:00-17:00 | Design Compendium Embedded System for AMD XIlinx devices | so-logic | Virtual Learning Environment (Online) | € 4,250.00 | |
07.08. - 08.08.2025 09:00-17:00 | Operating Systems and Hypervisors in Adaptive SoCs | Xilinx | Virtual Learning Environment (Online) | € 1,700.00 | |
05.08. - 06.08.2025 09:00-17:00 | Embedded Heterogeneous Design | Xilinx | Virtual Learning Environment (Online) | € 1,700.00 | |
04.08. - 08.08.2025 09:00-17:00 | Design Compendium with High Level Synthesis for AMD Xilinx devices | so-logic | Virtual Learning Environment (Online) | € 4,250.00 | |
31.07. - 01.08.2025 09:00-17:00 | Verification with SystemVerilog | Xilinx | Virtual Learning Environment (Online) | € 1,700.00 | |
28.07. - 30.07.2025 09:00-17:00 | Designing with Verilog | Xilinx | Virtual Learning Environment (Online) | € 1,700.00 | |
28.07. - 29.07.2025 09:00-17:00 | Designing with SystemVerilog | Xilinx | Virtual Learning Environment (Online) | € 1,700.00 | |
28.07. - 01.08.2025 09:00-17:00 | Design Compendium Verification with VHDL for AMD Xilinx devices | so-logic | Virtual Learning Environment (Online) | € 4,250.00 | |
27.07. - 28.07.2025 09:00-17:00 | Vitis Model Composer: A MATLAB and Simulink-based Product | Xilinx | Virtual Learning Environment (Online) | € 1,700.00 | |
21.07. - 25.07.2025 09:00-17:00 | Design Compendium Yocto for AMD Xilinx devices | so-logic | Virtual Learning Environment (Online) | € 4,250.00 | |
17.07. - 18.07.2025 09:00-17:00 | Designing FPGAs Using the Vivado Design Suite 4 | Xilinx | Virtual Learning Environment (Online) | € 1,700.00 | |
15.07. - 16.07.2025 09:00-17:00 | Designing FPGAs Using the Vivado Design Suite 3 | Xilinx | Virtual Learning Environment (Online) | € 1,700.00 | |
15.07. - 16.07.2025 09:00-17:00 | Designing FPGAs Using the Vivado Design Suite 1 | Xilinx | Virtual Learning Environment (Online) | € 1,700.00 | |
14.07. - 18.07.2025 09:00-17:00 | Design Compendium with Verilog for AMD Xilinx devices | so-logic | Virtual Learning Environment (Online) | € 4,250.00 | |
10.07. - 11.07.2025 09:00-17:00 | Designing FPGAs Using the Vivado Design Suite 2 | Xilinx | Virtual Learning Environment (Online) | € 1,700.00 | |
07.07. - 09.07.2025 09:00-17:00 | Design Compendium with VHDL for AMD Xilinx devices | so-logic | Virtual Learning Environment (Online) | € 4,250.00 | |
03.07. - 04.07.2025 09:00-17:00 | Designing an Integrated PCI Express System | Xilinx | Virtual Learning Environment (Online) | € 1,700.00 | |
01.07. - 02.07.2025 09:00-17:00 | Designing with the Versal Adaptive SoC: PCI Express Systems | Xilinx | Virtual Learning Environment (Online) | € 1,700.00 | |
30.06. - 04.07.2025 09:00-17:00 | Design Compendium with SystemC for AMD Xilinx devices | so-logic | Virtual Learning Environment (Online) | € 4,250.00 | |
30.06. - 30.06.2025 09:00-17:00 | PCIe Protocol | Xilinx | Virtual Learning Environment (Online) | € 850.00 | |
26.06. - 27.06.2025 09:00-17:00 | Designing with the Versal Adaptive SoC: Power and Board Design | Xilinx | Virtual Learning Environment (Online) | € 1,700.00 | |
24.06. - 25.06.2025 09:00-17:00 | Designing with the Versal Adaptive SoC: Memory Interfaces | Xilinx | Virtual Learning Environment (Online) | € 1,700.00 | |
23.06. - 23.06.2025 09:00-17:00 | Designing with the Versal Adaptive SoC: Network on Chip | Xilinx | Virtual Learning Environment (Online) | € 850.00 | |
18.06. - 19.06.2025 09:00-17:00 | Designing with the Versal Adaptive SoC: Hardware Debug | Xilinx | Virtual Learning Environment (Online) | € 1,700.00 | |
17.06. - 18.06.2025 09:00-17:00 | Designing with the Versal Adaptive SoC: Architecture | Xilinx | Virtual Learning Environment (Online) | € 1,700.00 | |
16.06. - 20.06.2025 09:00-17:00 | Design Compendium with High Level Synthesis for AMD Xilinx devices | so-logic | Virtual Learning Environment (Online) | € 4,250.00 | |
12.06. - 13.06.2025 09:00-17:00 | Developing AI Inference Solutions with the Vitis AI Platform | Xilinx | Virtual Learning Environment (Online) | € 1,700.00 | |
10.06. - 11.06.2025 09:00-17:00 | Designing with Versal AI Engine: Kernel Programming and Optimization - 3 | Xilinx | Virtual Learning Environment (Online) | € 1,700.00 | |
09.06. - 13.06.2025 09:00-17:00 | Design Compendium Verification with VHDL for AMD Xilinx devices | so-logic | Virtual Learning Environment (Online) | € 1,700.00 | |
05.06. - 06.06.2025 09:00-17:00 | Designing with Versal AI Engine: Graph Programming with AI Engine Kernels - 2 | Xilinx | Virtual Learning Environment (Online) | € 1,700.00 | |
03.06. - 04.06.2025 09:00-17:00 | Designing with Versal AI Engine: Architecture and Design Flow - 1 | Xilinx | Virtual Learning Environment (Online) | € 1,700.00 | |
02.06. - 06.06.2025 09:00-17:00 | Design Compendium Yocto for AMD Xilinx devices | so-logic | Virtual Learning Environment (Online) | € 4,250.00 | |
29.05. - 30.05.2025 09:00-17:00 | Designing with Ethernet MAC Controllers | Xilinx | Virtual Learning Environment (Online) | € 1,700.00 | |
28.05. - 28.05.2025 09:00-17:00 | Designing with the Versal Adaptive SoC: Serial Transceivers | Xilinx | Virtual Learning Environment (Online) | € 850.00 | |
26.05. - 30.05.2025 09:00-17:00 | Design Compendium with Verilog for AMD Xilinx devices | so-logic | Virtual Learning Environment (Online) | € 4,250.00 | |
26.05. - 27.05.2025 09:00-17:00 | Designing with Xilinx Serial Transceivers | Xilinx | Virtual Learning Environment (Online) | € 1,700.00 | |
22.05. - 23.05.2025 09:00-17:00 | DFX - Designing with Dynamic Function eXchange Using the Vivado Design Suite | Xilinx | so-logic (top1) (Austria) | € 1,700.00 | |
19.05. - 21.05.2025 09:00-17:00 | Design Compendium with VHDL for AMD Xilinx devices | so-logic | Virtual Learning Environment (Online) | € 4,250.00 | |
15.05. - 16.05.2025 09:00-17:00 | Embedded Design with PetaLinux Tools | Xilinx | Virtual Learning Environment (Online) | € 1,700.00 | |
13.05. - 14.05.2025 09:00-17:00 | Designing with the Zynq UltraScale+ RFSoC | Xilinx | Virtual Learning Environment (Online) | € 1,700.00 | |
12.05. - 16.05.2025 09:00-17:00 | Design Compendium Embedded System for AMD XIlinx devices | so-logic | Virtual Learning Environment (Online) | € 4,250.00 | |
08.05. - 09.05.2025 09:00-17:00 | Operating Systems and Hypervisors in Adaptive SoCs | Xilinx | Virtual Learning Environment (Online) | € 1,700.00 | |
06.05. - 07.05.2025 09:00-17:00 | Embedded Heterogeneous Design | Xilinx | Virtual Learning Environment (Online) | € 1,700.00 | |
05.05. - 09.05.2025 09:00-17:00 | Design Compendium with High Level Synthesis for AMD Xilinx devices | so-logic | Virtual Learning Environment (Online) | € 4,250.00 | |
01.05. - 02.05.2025 09:00-17:00 | Verification with SystemVerilog | Xilinx | Virtual Learning Environment (Online) | € 1,700.00 | |
29.04. - 30.04.2025 09:00-17:00 | Designing with SystemVerilog | Xilinx | Virtual Learning Environment (Online) | € 1,700.00 | |
28.04. - 30.04.2025 09:00-17:00 | Designing with Verilog | Xilinx | Virtual Learning Environment (Online) | € 1,700.00 | |
28.04. - 02.05.2025 09:00-17:00 | Design Compendium Verification with VHDL for AMD Xilinx devices | so-logic | Virtual Learning Environment (Online) | € 4,250.00 | |
24.04. - 25.04.2025 09:00-17:00 | Vitis Model Composer: A MATLAB and Simulink-based Product | Xilinx | Virtual Learning Environment (Online) | € 1,700.00 | |
23.04. - 27.04.2025 09:00-17:00 | Design Compendium Embedded System for AMD XIlinx devices | so-logic | Virtual Learning Environment (Online) | € 4,250.00 | |
22.04. - 23.04.2025 09:00-17:00 | High-Level Synthesis with the Vitis Unified IDE (HLS) | Xilinx | Virtual Learning Environment (Online) | € 1,700.00 | |
21.04. - 25.04.2025 09:00-17:00 | Design Compendium Yocto for AMD Xilinx devices | so-logic | Virtual Learning Environment (Online) | € 4,250.00 | |
17.04. - 18.04.2025 09:00-17:00 | Designing FPGAs Using the Vivado Design Suite 4 | Xilinx | Virtual Learning Environment (Online) | € 1,700.00 | |
15.04. - 17.04.2025 09:00-17:00 | Designing with VHDL | Xilinx | Virtual Learning Environment (Online) | € 2,250.00 | |
15.04. - 16.04.2025 09:00-17:00 | Designing FPGAs Using the Vivado Design Suite 3 | Xilinx | Virtual Learning Environment (Online) | € 1,700.00 | |
10.04. - 11.04.2025 09:00-17:00 | Designing FPGAs Using the Vivado Design Suite 2 | Xilinx | Virtual Learning Environment (Online) | € 1,700.00 | |
08.04. - 08.04.2025 09:00-17:00 | Designing FPGAs Using the Vivado Design Suite 1 | Xilinx | Virtual Learning Environment (Online) | € 1,700.00 | |
07.04. - 09.04.2025 09:00-17:00 | Design Compendium with VHDL for AMD Xilinx devices | so-logic | Virtual Learning Environment (Online) | € 4,250.00 | |
04.04. - 08.04.2025 09:00-17:00 | Design Compendium with Verilog for AMD Xilinx devices | so-logic | Virtual Learning Environment (Online) | € 4,250.00 | |
03.04. - 04.04.2025 09:00-17:00 | Designing an Integrated PCI Express System | Xilinx | Virtual Learning Environment (Online) | € 1,700.00 | |
01.04. - 02.04.2025 09:00-17:00 | Designing with the Versal Adaptive SoC: PCI Express Systems | Xilinx | Virtual Learning Environment (Online) | € 1,700.00 | |
31.03. - 04.04.2025 09:00-17:00 | Design Compendium with SystemC for AMD Xilinx devices | so-logic | Virtual Learning Environment (Online) | € 4,250.00 | |
27.03. - 28.03.2025 09:00-17:00 | Designing with the Versal Adaptive SoC: Power and Board Design | Xilinx | Virtual Learning Environment (Online) | € 1,700.00 | |
25.03. - 26.03.2025 09:00-17:00 | Designing with the Versal Adaptive SoC: Memory Interfaces | Xilinx | Virtual Learning Environment (Online) | € 1,700.00 | |
24.03. - 24.03.2025 09:00-17:00 | Designing with the Versal Adaptive SoC: Network on Chip | Xilinx | Virtual Learning Environment (Online) | € 850.00 | |
24.03. - 28.03.2025 09:00-17:00 | Design Compendium Embedded System for AMD XIlinx devices | so-logic | Virtual Learning Environment (Online) | € 4,250.00 | |
19.03. - 20.03.2025 09:00-17:00 | Designing with the Versal Adaptive SoC: Hardware Debug | Xilinx | Virtual Learning Environment (Online) | € 1,700.00 | |
18.03. - 19.03.2025 09:00-17:00 | Designing with the Versal Adaptive SoC: Architecture | Xilinx | Virtual Learning Environment (Online) | € 1,700.00 | |
17.03. - 21.03.2025 09:00-17:00 | Design Compendium with High Level Synthesis for AMD Xilinx devices | so-logic | Virtual Learning Environment (Online) | € 4,250.00 | |
13.03. - 14.03.2025 09:00-17:00 | Developing AI Inference Solutions with the Vitis AI Platform | Xilinx | Virtual Learning Environment (Online) | € 1,700.00 | |
12.03. - 12.03.2025 09:00-17:00 | PCIe Protocol | Xilinx | Virtual Learning Environment (Online) | € 850.00 | |
11.03. - 12.03.2025 09:00-17:00 | Designing with Versal AI Engine: Kernel Programming and Optimization - 3 | Xilinx | Virtual Learning Environment (Online) | € 1,700.00 | |
10.03. - 14.03.2025 09:00-17:00 | Design Compendium Verification with VHDL for AMD Xilinx devices | so-logic | Virtual Learning Environment (Online) | € 1,700.00 | |
06.03. - 07.03.2025 09:00-17:00 | Designing with Versal AI Engine: Graph Programming with AI Engine Kernels - 2 | Xilinx | Virtual Learning Environment (Online) | € 1,700.00 | |
04.03. - 05.03.2025 09:00-17:00 | Designing with Versal AI Engine: Architecture and Design Flow - 1 | Xilinx | Virtual Learning Environment (Online) | € 1,700.00 | |
03.03. - 07.03.2025 09:00-17:00 | Design Compendium Yocto for AMD Xilinx devices | so-logic | Virtual Learning Environment (Online) | € 4,250.00 | |
27.02. - 28.02.2025 09:00-17:00 | Designing with Ethernet MAC Controllers | Xilinx | Virtual Learning Environment (Online) | € 1,700.00 | |
26.02. - 26.02.2025 09:00-17:00 | Designing with the Versal Adaptive SoC: Serial Transceivers | Xilinx | Virtual Learning Environment (Online) | € 850.00 | |
24.02. - 28.02.2025 09:00-17:00 | Design Compendium with Verilog for AMD Xilinx devices | so-logic | Virtual Learning Environment (Online) | € 4,250.00 | |
24.02. - 25.02.2025 09:00-17:00 | Designing with Xilinx Serial Transceivers | Xilinx | Virtual Learning Environment (Online) | € 1,700.00 | |
20.02. - 21.02.2025 09:00-17:00 | DFX - Designing with Dynamic Function eXchange Using the Vivado Design Suite | Xilinx | Virtual Learning Environment (Online) | € 1,700.00 | |
13.02. - 14.02.2025 09:00-17:00 | Embedded Design with PetaLinux Tools | Xilinx | Virtual Learning Environment (Online) | € 1,700.00 | |
12.02. - 13.02.2025 09:00-17:00 | Designing with the Zynq UltraScale+ RFSoC | Xilinx | Virtual Learning Environment (Online) | € 1,700.00 | |
10.02. - 10.02.2025 09:00-16:00 | C++ for Adaptive SOC | Xilinx | Virtual Learning Environment (Online) | € 0.00 | |
10.02. - 14.02.2025 09:00-17:00 | Design Compendium Embedded System for AMD XIlinx devices | so-logic | Virtual Learning Environment (Online) | € 4,250.00 | |
06.02. - 07.02.2025 09:00-17:00 | Operating Systems and Hypervisors in Adaptive SoCs | Xilinx | Virtual Learning Environment (Online) | € 1,700.00 | |
04.02. - 05.02.2025 09:00-17:00 | Embedded Heterogeneous Design | Xilinx | Virtual Learning Environment (Online) | € 1,700.00 | |
03.02. - 07.02.2025 09:00-17:00 | Design Compendium with High Level Synthesis for AMD Xilinx devices | so-logic | Virtual Learning Environment (Online) | € 4,250.00 | |
28.01. - 29.01.2025 09:00-17:00 | Designing with SystemVerilog | Xilinx | Virtual Learning Environment (Online) | € 1,700.00 | |
27.01. - 29.01.2025 09:00-17:00 | Designing with Verilog | Xilinx | Virtual Learning Environment (Online) | € 1,700.00 | |
27.01. - 31.01.2025 09:00-17:00 | Design Compendium Verification with VHDL for AMD Xilinx devices | so-logic | Virtual Learning Environment (Online) | € 4,250.00 | |
27.01. - 28.01.2025 09:00-17:00 | Verification with SystemVerilog | Xilinx | Virtual Learning Environment (Online) | € 1,700.00 |