|
03.04. - 04.04.2023 09:00-17:00
|
Advanced VHDL
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 1,600.00
|
Add to cart
|
|
04.04. - 06.04.2023 09:00-17:00
|
Designing with the Zynq UltraScale+ RFSoC
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 2,250.00
|
Add to cart
|
|
05.04. - 06.04.2023 09:00-17:00
|
Zynq UltraScale+ MPSoC for the System Architect
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 1,600.00
|
Add to cart
|
|
05.04. - 06.04.2023 09:00-17:00
|
Zynq UltraScale+ MPSoC for the Software Developer
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 1,600.00
|
Add to cart
|
|
11.04. - 13.04.2023 09:00-17:00
|
Designing with Multi-Gigabit Serial I/O
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 2,400.00
|
Add to cart
|
|
11.04. - 12.04.2023 09:00-17:00
|
Designing with Ethernet MAC Controllers
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 1,600.00
|
Add to cart
|
|
12.04. - 12.04.2023 09:00-17:00
|
Advanced Features and Techniques of Embedded Systems Software Design
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 800.00
|
Add to cart
|
|
12.04. - 12.04.2023 09:00-17:00
|
Zynq UltraScale+ MPSoC for the Hardware Designer
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 800.00
|
Add to cart
|
|
17.04. - 18.04.2023 09:00-17:00
|
Designing a LogiCORE PCI Express System
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 1,600.00
|
Add to cart
|
|
17.04. - 18.04.2023 09:00-17:00
|
Designing with UltraScale FPGA Transceivers
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 1,600.00
|
Add to cart
|
|
17.04. - 19.04.2023 09:00-17:00
|
FPGA Design with SystemC Basic
|
so-logic
|
so-logic (top1) (Austria)
|
€ 2,400.00
|
Add to cart
|
|
17.04. - 17.04.2023 09:00-17:00
|
PCIe Protocol
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 800.00
|
Add to cart
|
|
17.04. - 19.04.2023 09:00-17:00
|
Signal Integrity and Board Design for Xilinx FPGAs
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 2,400.00
|
Add to cart
|
|
20.04. - 21.04.2023 09:00-17:00
|
Designing with Xilinx Serial Transceivers
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 1,600.00
|
Add to cart
|
|
24.04. - 25.04.2023 09:00-17:00
|
Designing with Xilinx 7 Series Families
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 1,600.00
|
Add to cart
|
|
24.04. - 25.04.2023 09:00-17:00
|
Designing FPGAs Using the Vivado Design Suite 1
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 1,600.00
|
Add to cart
|
|
26.04. - 27.04.2023 09:00-17:00
|
Designing FPGAs Using the Vivado Design Suite 2
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 1,600.00
|
Add to cart
|
|
26.04. - 28.04.2023 09:00-17:00
|
Designing with the Spartan-6 and Virtex-6 Families
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 2,400.00
|
Add to cart
|
|
28.04. - 28.04.2023 09:00-17:00
|
Designing with the Virtex-5 FPGA Family
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 800.00
|
Add to cart
|
|
02.05. - 03.05.2023 09:00-17:00
|
Accelerating C, C++, OpenCL, and RTL Applications with the SDAccel Environment
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 1,600.00
|
Add to cart
|
|
02.05. - 03.05.2023 09:00-17:00
|
Designing FPGAs Using the Vivado Design Suite 3
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 1,600.00
|
Add to cart
|
|
04.05. - 05.05.2023 09:00-17:00
|
Partial Reconfiguration
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 1,600.00
|
Add to cart
|
|
04.05. - 04.05.2023 09:00-17:00
|
C-based HLS Coding for Software Designers
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 800.00
|
Add to cart
|
|
05.05. - 05.05.2023 09:00-17:00
|
C-based HLS Coding for Hardware Designers
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 800.00
|
Add to cart
|
|
08.05. - 09.05.2023 09:00-17:00
|
Zynq SoC System Architecture
|
|
so-logic (top1) (Austria)
|
€ 1,600.00
|
Add to cart
|
|
08.05. - 09.05.2023 09:00-17:00
|
C-based Design: High-Level Synthesis with Vivado HLS
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 1,600.00
|
Add to cart
|
|
09.05. - 12.05.2023 09:00-17:00
|
Designing with the Versal Adaptive SoC: Architecture and Methodology
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 3,200.00
|
Add to cart
|
|
09.05. - 10.05.2023 09:00-17:00
|
Designing FPGAs Using the Vivado Design Suite 4
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 1,600.00
|
Add to cart
|
|
10.05. - 12.05.2023 09:00-17:00
|
Designing with the UltraScale and UltraScale+ Architectures
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 2,400.00
|
Add to cart
|
|
12.05. - 12.05.2023 09:00-17:00
|
Developing AWS F1 Applications Using the SDAccel Environment
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 800.00
|
Add to cart
|
|
15.05. - 16.05.2023 09:00-17:00
|
Essential DSP Implementation Techniques for Xilinx FPGAs
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 1,600.00
|
Add to cart
|
|
15.05. - 16.05.2023 09:00-17:00
|
Designing with the Versal Adaptive SoC: PCI Express Systems
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 1,600.00
|
Add to cart
|
|
16.05. - 17.05.2023 09:00-17:00
|
Developing and Optimizing Applications Using the OpenCL Framework for FPGAs
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 1,600.00
|
Add to cart
|
|
17.05. - 17.05.2023 09:00-17:00
|
Designing with the Versal Adaptive SoC: Network on Chip
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 800.00
|
Add to cart
|
|
19.05. - 19.05.2023 09:00-17:00
|
Embedded C/C++ SDSoC Development Environment and Methodology
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 800.00
|
Add to cart
|
|
22.05. - 23.05.2023 09:00-17:00
|
DSP Design Using System Generator
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 1,600.00
|
Add to cart
|
|
22.05. - 24.05.2023 09:00-17:00
|
Designing with Verilog
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 2,400.00
|
Add to cart
|
|
22.05. - 24.05.2023 09:00-17:00
|
Designing with VHDL
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 2,400.00
|
Add to cart
|
|
23.05. - 24.05.2023 09:00-17:00
|
Designing with System Verilog
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 1,600.00
|
Add to cart
|
|
25.05. - 26.05.2023 09:00-17:00
|
Advanced VHDL
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 1,600.00
|
Add to cart
|
|
25.05. - 26.05.2023 09:00-17:00
|
Verification with System Verilog
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 1,600.00
|
Add to cart
|
|
30.05. - 01.06.2023 09:00-17:00
|
FPGA Design with Verilog Basic
|
so-logic
|
so-logic (top1) (Austria)
|
€ 2,400.00
|
Add to cart
|
|
30.05. - 01.06.2023 09:00-17:00
|
FPGA Design with VHDL Basic
|
so-logic
|
so-logic (top1) (Austria)
|
€ 2,400.00
|
Add to cart
|
|
30.05. - 01.06.2023 09:00-17:00
|
Embedded Open-Source Linux Development
|
so-logic
|
so-logic (top1) (Austria)
|
€ 2,400.00
|
Add to cart
|
|
01.06. - 02.06.2023 09:00-17:00
|
Advanced Features and Techniques of Embedded Systems Design
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 1,600.00
|
Add to cart
|
|
01.06. - 02.06.2023 09:00-17:00
|
Embedded Systems Design
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 1,600.00
|
Add to cart
|
|
05.06. - 06.06.2023 09:00-17:00
|
Designing with Versal AI Engine 1 - Architecture and Design Flow
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 1,600.00
|
Add to cart
|
|
05.06. - 06.06.2023 09:00-17:00
|
Yocto Basic
|
so-logic
|
so-logic (top1) (Austria)
|
€ 1,600.00
|
Add to cart
|
|
07.06. - 09.06.2023 09:00-17:00
|
Designing with Versal AI Engine 2: Graph Programming with AI Engine Kernels
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 2,400.00
|
Add to cart
|
|
07.06. - 07.06.2023 09:00-17:00
|
Yocto Advanced
|
so-logic
|
so-logic (top1) (Austria)
|
€ 800.00
|
Add to cart
|
|
12.06. - 13.06.2023 09:00-17:00
|
Zynq UltraScale+ MPSoC for the System Architect
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 1,600.00
|
Add to cart
|
|
12.06. - 14.06.2023 09:00-17:00
|
Designing with Versal AI Engine 3: Kernel Programming and Optimization
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 2,400.00
|
Add to cart
|
|
14.06. - 15.06.2023 09:00-17:00
|
Zynq UltraScale+ MPSoC for the Software Developer
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 1,600.00
|
Add to cart
|
|
14.06. - 15.06.2023 09:00-17:00
|
Embedded Systems Software Design
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 1,600.00
|
Add to cart
|
|
16.06. - 16.06.2023 09:00-17:00
|
Zynq UltraScale+ MPSoC for the Hardware Designer
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 800.00
|
Add to cart
|
|
19.06. - 21.06.2023 09:00-17:00
|
FPGA Design with SystemC Basic
|
so-logic
|
so-logic (top1) (Austria)
|
€ 2,400.00
|
Add to cart
|
|
19.06. - 20.06.2023 09:00-17:00
|
Designing with Ethernet MAC Controllers
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 1,600.00
|
Add to cart
|
|
19.06. - 21.06.2023 09:00-17:00
|
Designing with Multi-Gigabit Serial I/O
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 2,400.00
|
Add to cart
|
|
19.06. - 19.06.2023 09:00-17:00
|
Advanced Features and Techniques of Embedded Systems Software Design
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 800.00
|
Add to cart
|
|
21.06. - 22.06.2023 09:00-17:00
|
Designing a LogiCORE PCI Express System
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 1,600.00
|
Add to cart
|
|
22.06. - 23.06.2023 09:00-17:00
|
Designing with UltraScale FPGA Transceivers
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 1,600.00
|
Add to cart
|
|
26.06. - 27.06.2023 09:00-17:00
|
Vivado Design Suite for ISE Project Navigator Users
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 1,600.00
|
Add to cart
|
|
26.06. - 27.06.2023 09:00-17:00
|
Designing FPGAs Using the Vivado Design Suite 1
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 1,600.00
|
Add to cart
|
|
26.06. - 26.06.2023 13:00-21:00
|
Vitis Design flow
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 0.00
|
Add to cart
|
|
28.06. - 29.06.2023 09:00-17:00
|
Designing FPGAs Using the Vivado Design Suite 2
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 1,600.00
|
Add to cart
|
|
30.06. - 30.06.2023 09:00-17:00
|
Vivado Design Suite for ISE Software Project Navigator Users
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 800.00
|
Add to cart
|
|
30.06. - 30.06.2023 09:00-17:00
|
UltraFast Design Methodology
|
Xilinx
|
so-logic (top1) (Austria)
|
€ 800.00
|
Add to cart
|
