Training schedules 2022-07-05 - 2023-07-05
Event period | Training | Partner | Location | Price | |
---|---|---|---|---|---|
07.07. - 08.07.2022 09:00-17:00 | Partial Reconfiguration | Xilinx | so-logic (top1) (Austria) | € 1,500.00 | |
12.07. - 13.07.2022 09:00-17:00 | C-based Design: High-Level Synthesis with Vivado HLS | Xilinx | so-logic (top1) (Austria) | € 1,500.00 | |
22.07. - 22.07.2022 09:00-17:00 | Developing AWS F1 Applications Using the SDAccel Environment | Xilinx | so-logic (top1) (Austria) | € 750.00 | |
25.07. - 26.07.2022 09:00-17:00 | Essential DSP Implementation Techniques for Xilinx FPGAs | Xilinx | so-logic (top1) (Austria) | € 1,500.00 | |
27.07. - 28.07.2022 09:00-17:00 | DSP Design Using System Generator | Xilinx | so-logic (top1) (Austria) | € 1,500.00 | |
01.08. - 01.08.2022 09:00-17:00 | Designing with Verilog | Xilinx | so-logic (top1) (Austria) | € 750.00 | |
01.08. - 03.08.2022 09:00-17:00 | Designing with VHDL | Xilinx | so-logic (top1) (Austria) | € 2,250.00 | |
04.08. - 05.08.2022 09:00-17:00 | Verification with System Verilog | Xilinx | so-logic (top1) (Austria) | € 1,500.00 | |
04.08. - 05.08.2022 09:00-17:00 | Advanced VHDL | Xilinx | so-logic (top1) (Austria) | € 1,500.00 | |
08.08. - 09.08.2022 09:00-17:00 | Zynq UltraScale+ MPSoC for the System Architect | Xilinx | so-logic (top1) (Austria) | € 1,500.00 | |
09.08. - 10.08.2022 09:00-17:00 | Zynq All Programmable SoC System Architecture | Xilinx | so-logic (top1) (Austria) | € 1,500.00 | |
10.08. - 11.08.2022 09:00-17:00 | Migrating to the Vitis Embedded Software Development IDE Workshop | Xilinx | so-logic (top1) (Austria) | € 1,500.00 | |
10.08. - 11.08.2022 09:00-17:00 | Zynq UltraScale+ MPSoC for the Software Developer | Xilinx | so-logic (top1) (Austria) | € 1,500.00 | |
10.08. - 11.08.2022 09:00-17:00 | Embedded Systems Software Design | Xilinx | so-logic (top1) (Austria) | € 1,500.00 | |
11.08. - 12.08.2022 09:00-17:00 | Designing with the Zynq UltraScale+ RFSoC | Xilinx | so-logic (top1) (Austria) | € 1,500.00 | |
12.08. - 12.08.2022 09:00-17:00 | Advanced Features and Techniques of Embedded Systems Software Design | Xilinx | so-logic (top1) (Austria) | € 750.00 | |
12.08. - 12.08.2022 09:00-17:00 | Zynq UltraScale+ MPSoC for the Hardware Designer | Xilinx | so-logic (top1) (Austria) | € 750.00 | |
15.08. - 16.08.2022 09:00-17:00 | Designing with Ethernet MAC Controllers | Xilinx | so-logic (top1) (Austria) | € 1,500.00 | |
15.08. - 17.08.2022 09:00-17:00 | Designing with Multi-Gigabit Serial I/O | Xilinx | so-logic (top1) (Austria) | € 2,250.00 | |
17.08. - 18.08.2022 09:00-17:00 | Designing with UltraScale FPGA Transceivers | Xilinx | so-logic (top1) (Austria) | € 1,500.00 | |
18.08. - 19.08.2022 09:00-17:00 | Designing a LogiCORE PCI Express System | Xilinx | so-logic (top1) (Austria) | € 1,500.00 | |
22.08. - 23.08.2022 09:00-17:00 | Designing FPGAs Using the Vivado Design Suite 1 | Xilinx | so-logic (top1) (Austria) | € 1,500.00 | |
24.08. - 25.08.2022 09:00-17:00 | Designing FPGAs Using the Vivado Design Suite 2 | Xilinx | so-logic (top1) (Austria) | € 1,500.00 | |
29.08. - 30.08.2022 09:00-17:00 | Designing FPGAs Using the Vivado Design Suite 3 | Xilinx | so-logic (top1) (Austria) | € 1,500.00 | |
01.09. - 01.09.2022 09:00-17:00 | Designing FPGAs Using the Vivado Design Suite 4 | Xilinx | so-logic (top1) (Austria) | € 1,500.00 | |
01.09. - 02.09.2022 09:00-17:00 | Partial Reconfiguration | Xilinx | so-logic (top1) (Austria) | € 1,500.00 | |
12.09. - 13.09.2022 09:00-17:00 | C-based Design: High-Level Synthesis with Vivado HLS | Xilinx | so-logic (top1) (Austria) | € 1,500.00 | |
16.09. - 16.09.2022 09:00-17:00 | Developing AWS F1 Applications Using the SDAccel Environment | Xilinx | so-logic (top1) (Austria) | € 750.00 | |
26.09. - 27.09.2022 09:00-17:00 | Essential DSP Implementation Techniques for Xilinx FPGAs | Xilinx | so-logic (top1) (Austria) | € 1,500.00 | |
29.09. - 30.09.2022 09:00-17:00 | DSP Design Using System Generator | Xilinx | so-logic (top1) (Austria) | € 1,500.00 | |
03.10. - 05.10.2022 09:00-17:00 | Designing with VHDL | Xilinx | so-logic (top1) (Austria) | € 2,250.00 | |
03.10. - 03.10.2022 09:00-17:00 | Designing with Verilog | Xilinx | so-logic (top1) (Austria) | € 750.00 | |
04.10. - 05.10.2022 09:00-17:00 | Designing with System Verilog | Xilinx | so-logic (top1) (Austria) | € 1,500.00 | |
05.10. - 07.10.2022 09:00-17:00 | FPGA Design with VHDL Basic | so-logic | so-logic (top1) (Austria) | € 2,400.00 | |
05.10. - 07.10.2022 09:00-17:00 | FPGA Design with Verilog Basic | so-logic | so-logic (top1) (Austria) | € 2,400.00 | |
06.10. - 07.10.2022 09:00-17:00 | Advanced VHDL | Xilinx | so-logic (top1) (Austria) | € 1,500.00 | |
06.10. - 07.10.2022 09:00-17:00 | Verification with System Verilog | Xilinx | so-logic (top1) (Austria) | € 1,500.00 | |
10.10. - 11.10.2022 09:00-17:00 | Zynq UltraScale+ MPSoC for the System Architect | Xilinx | so-logic (top1) (Austria) | € 1,500.00 | |
11.10. - 12.10.2022 09:00-17:00 | Zynq All Programmable SoC System Architecture | Xilinx | so-logic (top1) (Austria) | € 1,500.00 | |
12.10. - 14.10.2022 09:00-17:00 | Embedded System Basic | so-logic | so-logic (top1) (Austria) | € 2,400.00 | |
12.10. - 13.10.2022 09:00-17:00 | Zynq UltraScale+ MPSoC for the Software Developer | Xilinx | so-logic (top1) (Austria) | € 1,500.00 | |
12.10. - 13.10.2022 09:00-17:00 | Embedded Systems Software Design | Xilinx | so-logic (top1) (Austria) | € 1,500.00 | |
13.10. - 14.10.2022 09:00-17:00 | Designing with the Zynq UltraScale+ RFSoC | Xilinx | so-logic (top1) (Austria) | € 1,500.00 | |
14.10. - 14.10.2022 09:00-17:00 | Zynq UltraScale+ MPSoC for the Hardware Designer | Xilinx | so-logic (top1) (Austria) | € 750.00 | |
14.10. - 14.10.2022 09:00-17:00 | Advanced Features and Techniques of Embedded Systems Software Design | Xilinx | so-logic (top1) (Austria) | € 750.00 | |
17.10. - 19.10.2022 09:00-17:00 | Designing with Multi-Gigabit Serial I/O | Xilinx | so-logic (top1) (Austria) | € 2,250.00 | |
17.10. - 18.10.2022 09:00-17:00 | Designing with Ethernet MAC Controllers | Xilinx | so-logic (top1) (Austria) | € 1,500.00 | |
20.10. - 21.10.2022 09:00-17:00 | Designing with UltraScale FPGA Transceivers | Xilinx | so-logic (top1) (Austria) | € 1,500.00 | |
20.10. - 21.10.2022 09:00-17:00 | Designing a LogiCORE PCI Express System | Xilinx | so-logic (top1) (Austria) | € 1,500.00 | |
24.10. - 25.10.2022 09:00-17:00 | Yocto Basic | so-logic | so-logic (top1) (Austria) | € 1,600.00 | |
25.10. - 26.10.2022 09:00-17:00 | Designing FPGAs Using the Vivado Design Suite 1 | Xilinx | so-logic (top1) (Austria) | € 1,500.00 | |
26.10. - 26.10.2022 09:00-17:00 | Yocto Advanced | so-logic | so-logic (top1) (Austria) | € 800.00 | |
27.10. - 28.10.2022 09:00-17:00 | Designing FPGAs Using the Vivado Design Suite 2 | Xilinx | so-logic (top1) (Austria) | € 1,500.00 | |
01.11. - 02.11.2022 09:00-17:00 | Designing FPGAs Using the Vivado Design Suite 3 | Xilinx | so-logic (top1) (Austria) | € 1,500.00 | |
03.11. - 03.11.2022 09:00-17:00 | Designing FPGAs Using the Vivado Design Suite 4 | Xilinx | so-logic (top1) (Austria) | € 1,500.00 | |
10.11. - 11.11.2022 09:00-17:00 | Partial Reconfiguration | Xilinx | so-logic (top1) (Austria) | € 1,500.00 | |
21.11. - 22.11.2022 09:00-17:00 | C-based Design: High-Level Synthesis with Vivado HLS | Xilinx | so-logic (top1) (Austria) | € 1,500.00 | |
21.11. - 22.11.2022 09:00-17:00 | FPGA Design with High Level Synthesis HLS Basic | so-logic | so-logic (top1) (Austria) | € 1,600.00 | |
25.11. - 25.11.2022 09:00-17:00 | Developing AWS F1 Applications Using the SDAccel Environment | Xilinx | so-logic (top1) (Austria) | € 750.00 | |
28.11. - 29.11.2022 09:00-17:00 | Essential DSP Implementation Techniques for Xilinx FPGAs | Xilinx | so-logic (top1) (Austria) | € 1,500.00 | |
29.11. - 30.11.2022 09:00-17:00 | DSP Design Using System Generator | Xilinx | so-logic (top1) (Austria) | € 1,500.00 | |
12.12. - 12.12.2022 09:00-17:00 | Designing with Verilog | Xilinx | so-logic (top1) (Austria) | € 750.00 | |
12.12. - 14.12.2022 09:00-17:00 | FPGA Design with VHDL Basic | so-logic | so-logic (top1) (Austria) | € 2,400.00 | |
12.12. - 14.12.2022 09:00-17:00 | Designing with VHDL | Xilinx | so-logic (top1) (Austria) | € 2,250.00 | |
14.12. - 16.12.2022 09:00-17:00 | FPGA Design with Verilog Basic | so-logic | so-logic (top1) (Austria) | € 2,400.00 | |
14.12. - 15.12.2022 09:00-17:00 | Designing with System Verilog | Xilinx | so-logic (top1) (Austria) | € 1,500.00 | |
15.12. - 16.12.2022 09:00-17:00 | Advanced VHDL | Xilinx | so-logic (top1) (Austria) | € 1,500.00 | |
15.12. - 16.12.2022 09:00-17:00 | Verification with System Verilog | Xilinx | so-logic (top1) (Austria) | € 1,500.00 | |
16.01. - 16.01.2023 09:00-17:00 | Versal Compendium 1 : Architecture | so-logic | so-logic (top1) (Austria) | € 750.00 | |
23.01. - 23.01.2023 09:00-17:00 | Designing with Versal AI Engine 2: Graph Programming with AI Engine Kernels | Xilinx | so-logic (top1) (Austria) | € 800.00 | |
30.01. - 30.01.2023 09:00-17:00 | Versal Compendium 3 : AI Engine | so-logic | so-logic (top1) (Austria) | € 800.00 | |
02.02. - 03.02.2023 09:00-17:00 | Zynq UltraScale+ MPSoC for the Software Developer | Xilinx | so-logic (top1) (Austria) | € 1,600.00 | |
21.02. - 23.02.2023 09:00-17:00 | Spartan-6 with ISE Migration to 7 Series with Vivado | Xilinx | so-logic (top1) (Austria) | € 2,400.00 | |
01.03. - 02.03.2023 09:00-17:00 | Yocto Basic | so-logic | so-logic (top1) (Austria) | € 1,600.00 | |
02.03. - 03.03.2023 09:00-17:00 | Partial Reconfiguration | Xilinx | so-logic (top1) (Austria) | € 1,600.00 | |
03.03. - 03.03.2023 09:00-17:00 | Yocto Advanced | so-logic | so-logic (top1) (Austria) | € 800.00 | |
03.03. - 03.03.2023 09:00-17:00 | Designing FPGAs Using the Vivado Design Suite 4 | Xilinx | so-logic (top1) (Austria) | € 800.00 | |
06.03. - 07.03.2023 09:00-17:00 | Designing FPGAs Using the Vivado Design Suite 3 | Xilinx | so-logic (top1) (Austria) | € 1,600.00 | |
13.03. - 14.03.2023 09:00-17:00 | FPGA Design with High Level Synthesis HLS Basic | so-logic | so-logic (top1) (Austria) | € 1,600.00 | |
13.03. - 14.03.2023 09:00-17:00 | C-based Design: High-Level Synthesis with Vivado HLS | Xilinx | so-logic (top1) (Austria) | € 1,600.00 | |
17.03. - 17.03.2023 09:00-17:00 | Developing AWS F1 Applications Using the SDAccel Environment | Xilinx | so-logic (top1) (Austria) | € 800.00 | |
20.03. - 21.03.2023 09:00-17:00 | Essential DSP Implementation Techniques for Xilinx FPGAs | Xilinx | so-logic (top1) (Austria) | € 1,600.00 | |
23.03. - 24.03.2023 09:00-17:00 | DSP Design Using System Generator | Xilinx | so-logic (top1) (Austria) | € 1,600.00 | |
27.03. - 29.03.2023 09:00-17:00 | FPGA Design with Verilog Basic | so-logic | so-logic (top1) (Austria) | € 2,400.00 | |
27.03. - 29.03.2023 09:00-17:00 | FPGA Design with VHDL Basic | so-logic | so-logic (top1) (Austria) | € 2,400.00 | |
27.03. - 29.03.2023 09:00-17:00 | Designing with VHDL | Xilinx | so-logic (top1) (Austria) | € 2,400.00 | |
27.03. - 27.03.2023 09:00-17:00 | Designing with Verilog | Xilinx | so-logic (top1) (Austria) | € 800.00 | |
30.03. - 31.03.2023 09:00-17:00 | Verification with System Verilog | Xilinx | so-logic (top1) (Austria) | € 1,600.00 | |
03.04. - 04.04.2023 09:00-17:00 | Advanced VHDL | Xilinx | so-logic (top1) (Austria) | € 1,600.00 | |
05.04. - 06.04.2023 09:00-17:00 | Designing with the Zynq UltraScale+ RFSoC | Xilinx | so-logic (top1) (Austria) | € 1,600.00 | |
05.04. - 06.04.2023 09:00-17:00 | Zynq UltraScale+ MPSoC for the Software Developer | Xilinx | so-logic (top1) (Austria) | € 1,600.00 | |
05.04. - 06.04.2023 09:00-17:00 | Zynq UltraScale+ MPSoC for the System Architect | Xilinx | so-logic (top1) (Austria) | € 1,600.00 | |
11.04. - 12.04.2023 09:00-17:00 | Designing with Ethernet MAC Controllers | Xilinx | so-logic (top1) (Austria) | € 1,600.00 | |
11.04. - 13.04.2023 09:00-17:00 | Designing with Multi-Gigabit Serial I/O | Xilinx | so-logic (top1) (Austria) | € 2,400.00 | |
12.04. - 12.04.2023 09:00-17:00 | Advanced Features and Techniques of Embedded Systems Software Design | Xilinx | so-logic (top1) (Austria) | € 800.00 | |
12.04. - 12.04.2023 09:00-17:00 | Zynq UltraScale+ MPSoC for the Hardware Designer | Xilinx | so-logic (top1) (Austria) | € 800.00 | |
13.04. - 14.04.2023 09:00-17:00 | Zynq All Programmable SoC System Architecture | Xilinx | so-logic (top1) (Austria) | € 1,600.00 | |
17.04. - 18.04.2023 09:00-17:00 | Designing with UltraScale FPGA Transceivers | Xilinx | so-logic (top1) (Austria) | € 1,600.00 | |
17.04. - 18.04.2023 09:00-17:00 | Designing a LogiCORE PCI Express System | Xilinx | so-logic (top1) (Austria) | € 1,600.00 | |
17.04. - 19.04.2023 09:00-17:00 | FPGA Design with SystemC Basic | so-logic | so-logic (top1) (Austria) | € 2,400.00 | |
24.04. - 25.04.2023 09:00-17:00 | Designing FPGAs Using the Vivado Design Suite 1 | Xilinx | so-logic (top1) (Austria) | € 1,600.00 | |
26.04. - 27.04.2023 09:00-17:00 | Designing FPGAs Using the Vivado Design Suite 2 | Xilinx | so-logic (top1) (Austria) | € 1,600.00 | |
02.05. - 03.05.2023 09:00-17:00 | Designing FPGAs Using the Vivado Design Suite 3 | Xilinx | so-logic (top1) (Austria) | € 1,600.00 | |
04.05. - 05.05.2023 09:00-17:00 | Partial Reconfiguration | Xilinx | so-logic (top1) (Austria) | € 1,600.00 | |
08.05. - 09.05.2023 09:00-17:00 | C-based Design: High-Level Synthesis with Vivado HLS | Xilinx | so-logic (top1) (Austria) | € 1,600.00 | |
09.05. - 09.05.2023 09:00-17:00 | Designing FPGAs Using the Vivado Design Suite 4 | Xilinx | so-logic (top1) (Austria) | € 800.00 | |
12.05. - 12.05.2023 09:00-17:00 | Developing AWS F1 Applications Using the SDAccel Environment | Xilinx | so-logic (top1) (Austria) | € 800.00 | |
15.05. - 16.05.2023 09:00-17:00 | Essential DSP Implementation Techniques for Xilinx FPGAs | Xilinx | so-logic (top1) (Austria) | € 1,600.00 | |
22.05. - 23.05.2023 09:00-17:00 | DSP Design Using System Generator | Xilinx | so-logic (top1) (Austria) | € 1,600.00 | |
22.05. - 22.05.2023 09:00-17:00 | Designing with Verilog | Xilinx | so-logic (top1) (Austria) | € 800.00 | |
22.05. - 24.05.2023 09:00-17:00 | Designing with VHDL | Xilinx | so-logic (top1) (Austria) | € 2,400.00 | |
23.05. - 24.05.2023 09:00-17:00 | Designing with System Verilog | Xilinx | so-logic (top1) (Austria) | € 1,600.00 | |
25.05. - 26.05.2023 09:00-17:00 | Advanced VHDL | Xilinx | so-logic (top1) (Austria) | € 1,600.00 | |
25.05. - 26.05.2023 09:00-17:00 | Verification with System Verilog | Xilinx | so-logic (top1) (Austria) | € 1,600.00 | |
30.05. - 01.06.2023 09:00-17:00 | FPGA Design with VHDL Basic | so-logic | so-logic (top1) (Austria) | € 2,400.00 | |
30.05. - 01.06.2023 09:00-17:00 | FPGA Design with Verilog Basic | so-logic | so-logic (top1) (Austria) | € 2,400.00 | |
12.06. - 13.06.2023 09:00-17:00 | Zynq UltraScale+ MPSoC for the System Architect | Xilinx | so-logic (top1) (Austria) | € 1,600.00 | |
13.06. - 14.06.2023 09:00-17:00 | Zynq All Programmable SoC System Architecture | Xilinx | so-logic (top1) (Austria) | € 1,600.00 | |
14.06. - 15.06.2023 09:00-17:00 | Zynq UltraScale+ MPSoC for the Software Developer | Xilinx | so-logic (top1) (Austria) | € 1,600.00 | |
14.06. - 15.06.2023 09:00-17:00 | Embedded Systems Software Design | Xilinx | so-logic (top1) (Austria) | € 1,600.00 | |
16.06. - 16.06.2023 09:00-17:00 | Zynq UltraScale+ MPSoC for the Hardware Designer | Xilinx | so-logic (top1) (Austria) | € 800.00 | |
17.06. - 17.06.2023 09:00-17:00 | Advanced Features and Techniques of Embedded Systems Software Design | Xilinx | so-logic (top1) (Austria) | € 800.00 | |
19.06. - 21.06.2023 09:00-17:00 | Designing with Multi-Gigabit Serial I/O | Xilinx | so-logic (top1) (Austria) | € 2,400.00 | |
19.06. - 21.06.2023 09:00-17:00 | FPGA Design with SystemC Basic | so-logic | so-logic (top1) (Austria) | € 2,400.00 | |
19.06. - 20.06.2023 09:00-17:00 | Designing with Ethernet MAC Controllers | Xilinx | so-logic (top1) (Austria) | € 1,600.00 | |
21.06. - 22.06.2023 09:00-17:00 | Designing a LogiCORE PCI Express System | Xilinx | so-logic (top1) (Austria) | € 1,600.00 | |
22.06. - 23.06.2023 09:00-17:00 | Designing with UltraScale FPGA Transceivers | Xilinx | so-logic (top1) (Austria) | € 1,600.00 | |
26.06. - 27.06.2023 09:00-17:00 | Designing FPGAs Using the Vivado Design Suite 1 | Xilinx | so-logic (top1) (Austria) | € 1,600.00 | |
28.06. - 29.06.2023 09:00-17:00 | Designing FPGAs Using the Vivado Design Suite 2 | Xilinx | so-logic (top1) (Austria) | € 1,600.00 |