Designing with Versal AI Engine 2: Graph Programming with AI Engine Kernels

Course Description

This course describes the system design flow and interfaces that can be used for data movements in the Versalâ„¢ AI Engine. It also demonstrates how to utilize the advanced MAC intrinsics, AI Engine library for faster development and advanced features in adaptive data flow (ADF) graph implementation, such as using streams, cascade stream, buffer location constraints, run-time parameterization and APIs to update and/read run-time parameters. The emphasis of this course is on:

  • Implementing a system-level design flow (PS + PL + AIE) and the supported simulation
  • Using an interface for data movement between the PL and AI Engine
  • Utilizing advanced MAC intrinsics to implement filters
  • Utilizing the AI Engine library for faster development
  • Applying advanced features for optimizing a system-level design

Release Date

December 2020

Level

Connectivity 3

Training Duration

3 days

Who Should Attend?

Software and hardware developers, system architects, and anyone who needs to accelerate their software applications using Xilinx devices

Prerequisites

  • Comfort with the C/C++ programming language
  • Software development flow
  • Vitis software for application acceleration development flow

Skills Gained

After completing this comprehensive training, you will have the necessary skills to:

  • Describe the system-level flow, which includes PS + PL + AIE (SW-HW-SW) designs
  • Describe the supported emulation for a system-level design
  • Describe the data movement between the PS, PL, and AI Engines
  • Describe the implementation of the AI Engine and programmable logic
  • Implement a system-level design for Versal ACAPs with the Vitis tool flow
  • Utilize advanced MAC intrinsic syntax and application-specific intrinsics such as DDS and FFT
  • Utilize the AI Engine DSP library for faster development
  • Apply location constraints on kernels and buffers in the AI Engine array
  • Apply runtime parameters to modify application behavior
  • Debug a system-level design

Course Outline



  • Application Partitioning on Versal ACAPs 1 (Review)
  • Application Partitioning on Versal ACAPs 2
  • ACAP Data Communications 1
  • ACAP Data Communications 2
  • System Design Flow
  • Introduction to Advanced Intrinsic Functions
  • Versal AI Engine DSP Library Overview
  • Advanced Graph Input Specifications 1
  • Advanced Graph Input Specifications 2
  • Versal AI Engine Application Debug and Trace

Event Schedule

No events found. Event request.

Partner

Xilinx
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