Designing with the Versal ACAP: PCI Express Systems

Course Description

This course introduces the features and capabilities of the PCIe® and Cache Coherent Interconnect blocks in the Versal™ architecture. Learn how to implement a Versal ACAP PCI Express® solution in custom applications to improve time to market.The emphasis of this course is on:

  • Describing the Xilinx PCI Express design methodology
  • Enumerating various Xilinx PCI Express core products
  • Selecting the PCI Express IP cores from the Vivado® Design Suite
  • GeneratingPCI Express example designs and simple applications
  • Identifying the advanced capabilities of the PCIe specification

Release Date

December 2020

Level

Connectivity 3

Training Duration

3 days

Who Should Attend?

  • Hardware designers who want to create applications using Xilinx IP cores for PCI Express.
  • Software engineers who want to understand the deeper workings of the Xilinx PCI Express solution.
  • System architects who want to leverage key Xilinx advantages related to performance, latency, and bandwidth in PCI Express applications.

Prerequisites

  • Experience with the PCI/PCIe specification protocol
  • Knowledge of VHDL or Verilog
  • Some experience with Xilinx implementation tools
  • Some experience with a simulation tool, preferably the Vivado® simulator
  • Moderate digital design experience

Skills Gained

After completing this comprehensive training, you will know how to:

  • Construct a basic PCI Express system by:
    • Selecting the appropriate IP for your application
    • Specifying requirements of an endpoint application
    • Connecting PCIe IPs with the user application
    • Utilizing PL and PS resources supporting PCI Express
    • Simulating and implementing PCI Express systems
  • Identify the advanced capabilities of the PCI Express specification protocol and feature set

Course Outline



  • Introduction to PCI Express
  • Versal ACAP PCIe Solutions Overview
  • PCIe Block Architecture and Functionality
  • PCIe Block Interfaces Overview
  • PCIe Block Requester Interfaces
  • PCIe Block Completer Interfaces
  • PCIe Block Customization
  • PCIe Block Testbench and Simulation
  • PCIe Block Implementation
  • PL PCIe Block Debugging Overview
  • Introduction to DMA
  • PL PCIe XDMA-Bridge Subsystem
  • CPM4 Architecture and Functionality
  • CPM Block Customization
  • CPM IP Use Cases
  • System Design Methodology

Event Schedule

so-logic (top1) (Austria)
  • 03.08. - 04.08.2021 09:00-17:00 — € 1,600.00 excl. VAT Add to cart

Partner

Xilinx
Updated at: 2021-07-18 15:59:33 +0200to the top