Designing with the Versal ACAP: Network on Chip

Course Description

This course introduces the Versal™ ACAP network on chip (NoC) to users familiar with Xilinx devices. Besides providing an overview of the major components in the Versal device, the course illustrates how the NoC is used to efficiently move data within the device. The emphasis of this course is on:

  • Enumerating the major components comprising the NoC architecture in the Versal ACAP
  • Implementing a basic design using the NoC
  • Configuring the NoC for efficient data movement

Release Date

December 2020

Training Duration

1 day

Who Should Attend?

Hardware developers and system architects whether migrating from existing Xilinx devices or starting out with the Versal ACAP devices

Prerequisites

  • Any Xilinx device architecture class
  • Familiarity with the Vivado® Design Suite

Skills Gained

After completing this comprehensive training, you will know how to:

  • Identify the major network on chip components in the Versal ACAP
  • Include the necessary components to access the NoC from the PL
  • Configure connection QoS for efficient data movement

Course Outline



  • Architecture Overview for Existing Xilinx Users
  • Versal ACAPs Compared to Zynq UltraScale+ Devices/li>
  • NoC Introduction and Concepts
  • NoC Architecture
  • Design Tool Flow Overview
  • NoC DDR Memory Controller
  • NoC Performance Tuning
  • System Design Migration

Event Schedule

No events found. Event request.

Partner

Xilinx
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