Developing and Optimizing Applications Using the OpenCL Framework for FPGAs
Audience
Software and hardware developers who want to develop OpenCL, C/C++, and RTL applications in the SDAccel development environment.
Prerequisites
Basic knowledge of C/C++
Course Description
Learn how to develop new applications written in OpenCL, C/C++, and RTL in the SDAccel™ development environment for use on AMD Xilinx FPGAs. Porting existing applications is also covered.
This course also demonstrates how to debug and profile OpenCL code using the SDAccel development environment. In addition, you will also learn how to maximize performance and efficiently utilize FPGA resources.
Skills Gained
After completing this comprehensive training, you will have the necessary skills to:
Identify parallel computing applications suitable for accelerating on FPGAs
Discover how the FPGA architecture lends itself to parallel computing
Write OpenCL programs for FPGAs
Examine the OpenCL execution model
Analyze the OpenCL memory model
Profile and debug OpenCL code using the SDAccel development environment
Discover how to maximize performance in FPGA fabric
Efficiently utilize FPGA memory resources
Utilize the SDAccel development environment
Rapidly develop FPGA applications using OpenCL
Port programs written in OpenCL for CPUs or GPUs to AMD Xilinx FPGAs
Course Outline
Day 1
Introduction to OpenCL
Comparison of CPU, GPU, and FPGA Architectures
OpenCL Support for AMD Xilinx FPGAs
FPGA Hardware Details
Introduction to the OpenCL API
Lab 1: Creating an OpenCL Program from Scratch
Creating an OpenCL Program from Scratch – Provides an overview of OpenCL API, memory transfers, and kernel enqueuer operations.
OpenCL Execution Model
Lab 2: Vector Addition
Vector Addition – Learn how to execute parallel kernels.
Memory Hierarchy
Profiling and Debugging
Lab 3: Pi by Monte Carlo Processes
Pi by Monte Carlo Processes – Implement the Pi by Monte Carlo processes.
Optimization
Lab 4: Maximizing Performance
Maximizing Performance – Use vector data types and increase bandwidth.
Lab 5: Optimizing Kernels
Optimizing Kernels – Use Loop Unrolling and Loop Pipelining.
Day 2
Using the SDAccel Development Environment: Coding, Compiling, Emulating, Profiling, and Debugging
Lab 6: Profiling and Debugging Using the SDAccel Development Environment GUI
Profiling and Debugging Using the SDAccel Development Environment GUI – Learn how to use interactive programming tools to improve performance and squash bugs.
Using Existing C/C++ Code as Kernels in OpenCL
Lab 7: Optimizing C/C++ Code for OpenCL
Optimizing C/C++ Code for OpenCL – Convert existing C/C++ code into a kernel that can be used by OpenCL
RTL IP as Kernels in OpenCL
Lab 8: Using an RTL Kernel
Using an RTL Kernel – Learn how to use existing, highly optimized IP in a new OpenCL application.
