Accelerating C, C++, OpenCL, and RTL Applications with the SDAccel Environment

Course Description

Learn how to develop, debug, and profile new or existing OpenCL™, C/C++, and RTL applications in the SDAccel™ development environment for use on AMD Xilinx FPGAs. Also learn how to run designs on the Alveo™ accelerator card using Nimbix Cloud. The focus is on learning how to utilize techniques in the SDAccel environment to:
 Reduce latency
 Utilize the massive parallelism inherent to FPGAs
 Optimize throughput
 Pipeline for performance
This course also provides an introduction to targeting the Alveo accelerator card.

Release Date

Sept 2012

Level

EMBD 2

Training Duration

2 days

Who Should Attend?

Anyone who needs to accelerate their software applications using FPGAs.

Prerequisites

▪ Basic knowledge of AMD Xilinx FPGA architecture
▪ Comfort with the C/C++ programming language

Software Tools

SDx™ development environment 2018.3.op

Hardware

Architecture: AMD Xilinx Kintex® UltraScale™ FPGA

Skills Gained

After completing this comprehensive training, you will know how to:

• Describe how the FPGA architecture lends itself to parallel computing
Profile and debug OpenCL API code using the SDAccel development environment
• Explain how the SDx development environment helps software developers to focus on applications
• Examine the OpenCL API execution model
• Analyze the OpenCL API memory model
• Apply host code optimization and kernel optimization techniques
• Move data efficiently between kernel and global memory
• Create kernels from C, C++, OpenCL, or RTL IP (using the RTL Kernel Wizard)

Course Outline

Day 1

• Introduction to the SDAccel Environment and OpenCL Framework {Lecture}
• SDx Tools Overview {Lecture, Lab}
• Makefile Flow {Lecture, Lab}
• Introduction to FPGAs {Lecture}
• Alveo Product Overview {Lecture}
• Alveo Partner Ecosystem Solutions Overview {Lecture}
• Introduction to Nimbix Cloud {Lecture}
• OpenCL Framework Fundamentals 1 {Lecture}
• OpenCL Framework Fundamentals 2 {Lecture, Lab}
• Synchronization {Lecture, Lab}

Day 2

• Introduction to NDRanges {Lecture}
• Working with NDRanges {Lecture, Lab}
• Profiling {Lecture}
• Debugging {Lecture}
• C-Based Kernels {Lecture}
• C-Based Kernel Optimization {Lecture}
• Optimization Methodologies {Lecture}
• Memory Transfer Optimization Techniques {Lecture}
• Kernel Optimization Techniques {Lecture, Lab}
• Using the RTL Kernel Wizard

Topic Descriptions

Day 1

• ▪ Introduction to the SDAccel Environment and OpenCL Framework – Explains how software engineers and application developers can benefit from the SDAccel development environment and Open Computing Language (OpenCL) framework.
• ▪ SDx Tools Overview – Describes the elements of the development flow, such as software emulation, hardware emulation, and system run as well as debugging support for the host code and kernel code.
• ▪ Makefile Flow – Introduces the SDAccel environment makefile flow, where the user manages the compilation of host code and kernel(s).
• ▪ Alveo Product Overview – Describes the Alveo Data Center accelerator cards and lists the advantages of these cards and the available software solutions stack.
• ▪ Alveo Partner Ecosystem Solutions Overview – Describes the partner solutions available in the cloud and on premises for Alveo Data Center accelerator cards.
• ▪ Introduction to Nimbix Cloud – Explains the Nimbix Cloud, availability of the Alveo Data Center accelerator cards in the Nimbix Cloud, and how to run the design on the Nimbix Cloud.
• ▪ Introduction to FPGAs – Describes fundamental information about FPGAs, which is required to guide the SDAccel tool to the best computational architecture for any algorithm.
• ▪ OpenCL Framework Fundamentals 1 – Describes OpenCL framework models such as the Platform model, Execution model, Memory model, and Programming model.
• ▪ OpenCL Framework Fundamentals 2 – Describes OpenCL framework components such as the OpenCL platform API, OpenCL run-time API, and OpenCL programming language.
• ▪ Synchronization – Describes OpenCL synchronization techniques such as events, barriers, blocking write/read, and the benefit of using out-of-order execution.

Day 2

• ▪ Introduction to NDRanges – Explains the basics of NDRange (N dimensional range) and the OpenCL execution model that defines how kernels execute with the NDRange definition.
• ▪ Working with NDRanges – Explains the host code and kernel code changes with respect to NDRange. Also explains how NDRange works and the best way to represent the work-group size for the FPGA architecture.